 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| User's Manual V831 TM 32-bit Microprocessor Hardware PD705101 Document No. U12273EJ4V0UM00 (4th edition) Date Published January 1999 N CP(K) (c) Printed in Japan 1997 [MEMO] 2 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. V830, V831, and V830 family are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United State and/or other countries. UNIX is a registered trademark licensed by X/Open Company Limited in the US and other countries. 3 The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M7 96. 5 4 MAJOR REVISIONS IN THIS EDITION Page p. 35 p. 50 p. 51 p. 64 p. 86 p. 92 p. 118 p. 123 p. 124 p. 141 p. 176 p. 178 p. 181 Change of 3.1 Internal Peripheral I/O Space Addition of 4.7 Interrupt Requests by External Input Pins Change of the description in 5.2 External I/O Cycle Change of the description in 5.5 (4) Classification by data bus width Change of the description in 6.2 Address Space and Block Addition of 6.4 Wait Control by READY pin Change of description in 8.7.3 Request from internal peripheral hardware Change of Figure 8-20. 16- to 32-Bit Data Bus Width (32-bit transfer bus sizing) Change of Figure 8-21. 16- to 16-Bit Data Bus Width (32-bit transfer bus sizing) Addition of Caution to 9.2.5 (2) (b) Starting transmission/reception Change of the description in 13.2.2 (3) Releasing by RESET pin input Change of the description in 13.3.2 (2) Releasing by RESET pin input Change of the description in 14.3 Reset Contents The mark shows major revised points. 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J98. 11 6 PREFACE Readers This manual is intended for user engineers who wish to understand the functions of the V831 (PD705101) and design application systems using it. Purpose Organization This manual explains the hardware functions of the V831 in the following organization. The volumes of the V831 User's Manual are available: hardware (this manual) and architecture (V830 Family Hardware * General * Pin Function * CPU Function * Internal peripheral function * Appendix TM User's Manual - Architecture) manuals. Architecture * Register Set * Data Set * Address Space * Instruction * Interrupt and exception How to Read This Manual It is assumed that the readers of this manual have a general knowledge of electricity, logic circuits, and microcomputers. To understand the instruction functions in detail Refer to the V830 Family User's Manual - Architecture. To check the detailed function of a register whose name is known Refer to Appendix A Register Index. To understand the overall functions of the V831 Read this manual in the order of Table of Contents. Legend Data significance: Left: higher digits, right: lower digits Active low: xxx (top bar over pin or signal name) Memory map address: Top: high-order, bottom: low-order Note : Explanation of part of text marked Note Caution : Item to be especially noted. Remark : Supplement Numeric notation: Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Prefix indicating power of 2 (address space and memory capacity): K (kilo) G (giga) : 2 = 1024 20 30 2 3 10 M (mega) : 2 = 1024 : 2 = 1024 7 Related documents The related documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such. Document related to V831 Document Name V831 User's manual - Hardware V830 Family User's Manual - Architecture V831 Data Sheet Document No. This manual U12496E U12979E Document related to development tools (user's manual) Document Name CA830 (C compiler) Operation (UNIX based) Operation (Windows based) Assembly language C language Project manager RX830 (real-time OS) ITRON1 Fundamental Installation Technical TM TM Document No. U11013E U11068E U11014E U11010E U11991E U11730E U11731E U11713E U13152E U13151E U13150E ITRON Ver. 3.0 Fundamental Installation Technical 8 CONTENTS CHAPTER 1 GENERAL ..................................................................................................................... 1.1 Features................................................................................................................................... 1.2 Application Fields................................................................................................................... 1.3 Ordering Information ............................................................................................................. 1.4 Pin Configuration (Top View) ................................................................................................ 1.5 Internal Block Configuration ................................................................................................. 1.6 Internal Units........................................................................................................................... CHAPTER 2 PIN FUNCTION ............................................................................................................ 2.1 Pin Function List .................................................................................................................... 2.2 Pin Status ................................................................................................................................ 2.3 Pin Function............................................................................................................................ 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 Address bus ............................................................................................................................... Data bus ..................................................................................................................................... Bus control signals ..................................................................................................................... System control signals ............................................................................................................... Interrupt control signals .............................................................................................................. DRAM control signals ................................................................................................................. DMA control signals ................................................................................................................... Real-time pulse control signals .................................................................................................. Serial control signals .................................................................................................................. 19 19 20 21 21 23 24 27 27 29 30 30 30 30 31 32 32 33 33 33 34 34 2.3.10 Port control signals..................................................................................................................... 2.3.11 Debug control signals................................................................................................................. CHAPTER 3 CPU FUNCTION .......................................................................................................... 3.1 Internal Peripheral I/O Space................................................................................................. 3.1.1 Notes .......................................................................................................................................... 35 35 36 3.2 CPU Core System Registers.................................................................................................. CHAPTER 4 INTERRUPT/EXCEPTION PROCESSING FUNCTION ............................................. 4.1 Interrupt/Exception Processing ............................................................................................ 4.1.1 4.2.1 4.3.1 4.3.2 Interrupt/exception processing types.......................................................................................... Servicing non-maskable interrupt............................................................................................... Maskable interrupt servicing format ........................................................................................... Priority of maskable interrupt...................................................................................................... 36 37 37 37 4.2 Non-Maskable Interrupt ......................................................................................................... 4.3 Maskable Interrupts................................................................................................................ 39 39 40 40 42 4.4 Exception Processing ............................................................................................................ 4.5 Restoring from Exception/Interrupt...................................................................................... 4.5.1 4.5.2 4.6.1 4.6.2 4.6.3 Restoring from exception/interrupt ............................................................................................. Restoring from fatal exception routine........................................................................................ Interrupt group priority register (IGP) ......................................................................................... Interrupt clear register (ICR)....................................................................................................... Interrupt request register (IRR) .................................................................................................. 43 44 44 44 4.6 Interrupt Control Registers ................................................................................................... 45 45 46 47 9 4.6.4 4.6.5 Interrupt request mask register (IMR)......................................................................................... ICU mode register (IMOD).......................................................................................................... 47 48 4.7 Interrupt Requests by External Input Pins........................................................................... CHAPTER 5 BUS CONTROL FUNCTION....................................................................................... 5.1 Features................................................................................................................................... 5.2 External I/O Cycle ................................................................................................................... 5.2.1 5.3.1 5.3.2 5.3.3 5.4.1 5.4.2 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 Byte access control .................................................................................................................... SRAM (ROM) single cycle .......................................................................................................... SRAM (ROM) burst cycle ........................................................................................................... Byte access control .................................................................................................................... Page-ROM single cycle .............................................................................................................. Page-ROM burst cycle................................................................................................................ DRAM single cycle ..................................................................................................................... DRAM burst cycle ....................................................................................................................... Timing control ............................................................................................................................. Byte access control .................................................................................................................... Refresh control ........................................................................................................................... 50 51 51 51 52 5.3 SRAM (ROM) Cycle................................................................................................................. 53 55 57 59 5.4 Page-ROM Cycle ..................................................................................................................... 60 60 60 5.5 DRAM Cycle ............................................................................................................................ 63 65 68 72 74 75 5.6 5.7 5.8 5.9 5.10 5.11 Idle State.................................................................................................................................. Bus Sizing ............................................................................................................................... Bus Hold Cycle ....................................................................................................................... Bus Arbitration........................................................................................................................ Write Buffer Operation .......................................................................................................... Memory Mapped I/O............................................................................................................... 77 77 82 83 84 84 85 85 86 87 87 88 89 90 91 CHAPTER 6 WAIT CONTROL FUNCTION ..................................................................................... 6.1 Features................................................................................................................................... 6.2 Address Space and Block...................................................................................................... 6.3 Wait Control Registers ........................................................................................................... 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.4.1 6.4.2 Bus cycle type control register (BCTC) ...................................................................................... Data bus width control register (DBC) ........................................................................................ Programmable wait control register 0 (PWC0) ........................................................................... Programmable wait control register 1 (PWC1) ........................................................................... Programmable idle control register (PIC) ................................................................................... Sampling timing of READY pin ................................................................................................... When using both READY pin and programmable wait ............................................................... 6.4 Wait Control by READY Pin ................................................................................................... 92 92 92 CHAPTER 7 MEMORY ACCESS CONTROL FUNCTION ............................................................. 7.1 Features................................................................................................................................... 7.2 DRAM Control Function ......................................................................................................... 7.2.1 7.2.2 7.2.3 7.2.4 Address multiplex function.......................................................................................................... Judgment of on-page/off-page ................................................................................................... DRAM configuration register (DRC) ........................................................................................... Refresh function ......................................................................................................................... 93 93 93 94 94 94 96 10 7.3 Page-ROM Control Function ................................................................................................. 7.3.1 Page-ROM configuration register (PRC) .................................................................................... 98 98 CHAPTER 8 DMA FUNCTION.......................................................................................................... 8.1 Features................................................................................................................................... 8.2 Configuration .......................................................................................................................... 8.3 DMA Control Registers .......................................................................................................... 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.4.1 8.4.2 8.5.1 8.5.2 DMA source address registers 0 through 3 (DSA0 through DSA3)............................................ DMA destination address registers 0 through 3 (DDA0 through DDA3)..................................... DMA byte count registers 0 through 3 (DBC0 through DBC3) ................................................... DMA channel control registers 0 through 3 (DCHC0 through DCHC3) ...................................... DMA control register (DC) .......................................................................................................... Single transfer mode .................................................................................................................. Demand transfer mode............................................................................................................... Two-cycle transfer ...................................................................................................................... Subject to transfer ...................................................................................................................... 99 99 100 101 101 103 104 106 109 8.4 Transfer Mode......................................................................................................................... 110 110 111 8.5 DMA Transfer Type and Subject to Transfer ....................................................................... 111 111 112 8.6 Priorities of DMA Channels ................................................................................................... 8.7 DMA Transfer Request........................................................................................................... 8.7.1 8.7.2 8.7.3 8.8.1 Request from DMARQ pin.......................................................................................................... Request from software ............................................................................................................... Request from internal peripheral hardware ................................................................................ TCn bit reference and DMA transfer end interrupt ..................................................................... 113 113 113 117 118 8.8 DMA Transfer End Interrupt .................................................................................................. 8.9 DMA Transfer End Output ..................................................................................................... 8.10 Abort ........................................................................................................................................ 8.10.1 Aborting by NMI signal .............................................................................................................. 8.10.2 Temporary stop by HLDRQ signal or refresh ............................................................................ 119 119 121 122 122 122 8.11 Bus Sizing during DMA Transfer .......................................................................................... CHAPTER 9 SERIAL INTERFACE FUNCTION .............................................................................. 9.1 Asynchronous Serial Interface (UART) ................................................................................ 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.3.1 9.3.2 General....................................................................................................................................... Features ..................................................................................................................................... Configuration .............................................................................................................................. Mode registers and control registers .......................................................................................... Interrupt requests ....................................................................................................................... Basic operation........................................................................................................................... Features ..................................................................................................................................... Configuration .............................................................................................................................. Mode registers and control registers .......................................................................................... Pin function................................................................................................................................. Basic operation........................................................................................................................... Configuration and function ......................................................................................................... Baud rate generator compare register (BRG0) .......................................................................... 123 125 125 125 126 127 128 134 135 9.2 Clocked Serial Interface (CSI) ............................................................................................... 137 137 137 138 140 140 9.3 Baud Rate Generator.............................................................................................................. 142 142 145 11 9.3.3 Baud rate generator prescaler mode register (BPRM0) ............................................................. 146 CHAPTER 10 TIMER/COUNTER FUNCTION ................................................................................... 147 10.1 Features................................................................................................................................... 147 10.2 Configuration .......................................................................................................................... 148 10.2.1 Timer 1 ....................................................................................................................................... 10.2.2 Timer 4 ....................................................................................................................................... 10.2.3 Capture/compare registers (CC10 through CC13) ..................................................................... 149 151 152 10.3 Timer/Counter Control Registers .......................................................................................... 10.3.1 Timer unit mode register (TUM1)................................................................................................ 10.3.2 Timer control register 1 (TMC1).................................................................................................. 10.3.3 Timer control register 4 (TMC4).................................................................................................. 10.3.4 Timer output control register (TOC1).......................................................................................... 10.3.5 ICU mode register (IMOD).......................................................................................................... 10.3.6 Timer overflow status register (TOVS) ....................................................................................... 154 154 156 157 158 159 159 10.4 Operation................................................................................................................................. 10.4.1 Timer 1 ....................................................................................................................................... 10.4.2 Timer 4 ....................................................................................................................................... 160 160 161 10.5 Notes........................................................................................................................................ CHAPTER 11 PORT FUNCTION ...................................................................................................... 11.1 Configuration .......................................................................................................................... 11.2 Port Control Register ............................................................................................................. 11.2.1 I/O port register (PORT) ............................................................................................................. 11.2.2 I/O mode register (PM) ............................................................................................................... 11.2.3 Port control mode register (PC) .................................................................................................. 162 165 165 167 167 167 168 CHAPTER 12 CLOCK GENERATION FUNCTION ......................................................................... 169 12.1 Configuration .......................................................................................................................... 169 12.2 Selecting Input Clock ............................................................................................................. 170 12.2.1 Lockup time ................................................................................................................................ 170 12.3 Clock Output Control ............................................................................................................. 12.3.1 Clock output disable mode ......................................................................................................... 170 170 12.4 Clock Control Registers......................................................................................................... 12.4.1 Clock control register (CGC)....................................................................................................... 12.4.2 PLL control register (PLLCR)...................................................................................................... 171 171 172 CHAPTER 13 STANDBY FUNCTION............................................................................................... 13.1 Standby Mode ......................................................................................................................... 13.2 HALT mode.............................................................................................................................. 13.2.1 Setting and operating status of HALT mode............................................................................... 13.2.2 Releasing HALT mode................................................................................................................ 173 173 174 174 175 13.3 STOP Mode.............................................................................................................................. 13.3.1 Setting and operating status of STOP mode .............................................................................. 13.3.2 Releasing STOP mode ............................................................................................................... 176 176 177 13.4 Ensuring Oscillation Stabilization Time .............................................................................. 178 12 CHAPTER 14 RESET/NMI CONTROL FUNCTION ........................................................................ 181 14.1 Features................................................................................................................................... 181 14.2 Non-Maskable Interrupt (NMI) ............................................................................................... 181 14.3 Reset........................................................................................................................................ 181 14.3.1 Pin function................................................................................................................................. 181 14.3.2 Initialize ...................................................................................................................................... 183 CHAPTER 15 DEBUG/TRACE FUNCTION ..................................................................................... 185 15.1 Features................................................................................................................................... 185 APPENDIX A APPENDIX B REGISTER INDEX...................................................................................................... 187 GENERAL INDEX ...................................................................................................... 189 13 LIST OF FIGURES (1/3) Figure No. 3-1 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 6-1 6-2 6-3 6-4 6-5 Title Page 35 39 41 43 44 44 45 46 47 47 49 52 53 54 56 58 61 62 64 64 66 67 69 70 71 72 73 75 76 76 77 78 79 80 81 82 86 87 88 89 90 Internal Peripheral I/O Map....................................................................................................................... Processing Flow of Non-Maskable Interrupt............................................................................................. Maskable Interrupt Servicing Flow............................................................................................................ Exception Processing Flow....................................................................................................................... Flow of Restoration from Exception/Interrupt ........................................................................................... Flow of Restoration from Fatal Exception Routine ................................................................................... Interrupt Group Priority Register (IGP) ..................................................................................................... Interrupt Clear Register (ICR)................................................................................................................... Interrupt Request Register (IRR) .............................................................................................................. Interrupt Request Mask Register (IMR) .................................................................................................... ICU Mode Register (IMOD)....................................................................................................................... External I/O Cycle (32-bit bus mode)........................................................................................................ Example of Connection of 16M ROM (1M x 16) (in 32-bit bus mode) ...................................................... Example of Connection of 1M SRAM (128K x 8) (in 32-bit bus mode)..................................................... SRAM (ROM) Single Cycle (32-bit bus mode).......................................................................................... SRAM (ROM) Burst Cycle ........................................................................................................................ Page-ROM Burst Cycle (32-bit bus mode) ............................................................................................... Page-ROM Burst Cycle (16-bit bus mode, 8-byte page size) ................................................................... Example of Connection with 16M EDO-DRAM (1M x 16) (in 16-bit bus mode)........................................ Example of Connection with 16M EDO-DRAM (1M x 16) (in 32-bit bus mode)........................................ DRAM Single 1-Clock CAS on-page/off-page Cycle (32-bit bus mode) ................................................... DRAM Single 2-Clock CAS on-page/off-page Cycle (32-bit bus mode) ................................................... DRAM Burst 1-Clock CAS off-page Cycle (32-bit bus mode) ................................................................... DRAM Burst 1-Clock CAS on-page Cycle (32-bit bus mode) ................................................................... DRAM Burst 2-Clock CAS off-page Cycle (32-bit bus mode) ................................................................... DRAM Burst 2-Clock CAS on-page Cycle (32-bit bus mode) ................................................................... DRAM Access Timing (burst off-page cycle) ............................................................................................ CBR Refresh Cycle (when RFW1, 0 = 01, RP = 1) .................................................................................. CBR Refresh Cycle (when RFW1, 0 = 00, RP = 0) .................................................................................. CBR Self-Refresh Cycle (when cleared by NMI, RP = 0) ......................................................................... CBR Self-Refresh Cycle (when cleared by RESET, RP = 0).................................................................... Additional Access in DRAM Single Cycle due to Bus Sizing .................................................................... Additional Access in DRAM Burst Cycle due to Bus Sizing...................................................................... Additional Access in I/O Cycle due to Bus Sizing..................................................................................... Additional Access in SRAM Single Cycle due to Bus Sizing .................................................................... Bus Hold Cycle ......................................................................................................................................... Address Space ......................................................................................................................................... Bus Cycle Type Control Register (BCTC) ................................................................................................ Data Bus Width Control Register (DBC) ................................................................................................... Programmable Wait Control Register 0 (PWC0) ...................................................................................... Programmable Wait Control Register 1 (PWC1) ...................................................................................... 14 LIST OF FIGURES (2/3) Figure No. 6-6 7-1 7-2 7-3 7-4 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 8-16 8-17 8-18 8-19 8-20 8-21 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 Title Page 91 94 95 97 98 100 101 102 103 104 105 106 109 110 110 111 112 114 115 116 117 119 120 121 123 124 127 128 130 131 132 133 135 137 138 139 140 142 145 146 Programmable Idle Control Register (PIC) ............................................................................................... Output of Row Address and Column Address .......................................................................................... DRAM Configuration Register (DRC) ....................................................................................................... Refresh Control Register (RFC) ............................................................................................................... Page-ROM Configuration Register (PRC) ................................................................................................ DMAC Block Diagram............................................................................................................................... DMA Source Address Registers 0H through 3H (DSA0H through DSA3H) ............................................. DMA Source Address Registers 0L through 3L (DSA0L through DSA3L) ............................................... DMA Destination Address Registers 0H through 3H (DDA0H through DDA3H) ...................................... DMA Destination Address Registers 0L through 3L (DDA0L through DDA3L) ........................................ DMA Byte Count Registers 0 through 3 (DBC0 through DBC3)............................................................... DMA Channel Control Registers 0 through 3 (DCHC0 through DCHC3) ................................................. DMA Control Register (DC) ...................................................................................................................... Example of Single Transfer 1 ................................................................................................................... Example of Single Transfer 2 ................................................................................................................... Example of Demand Transfer................................................................................................................... Two-Cycle Demand Transfer (external I/O to DRAM (on-page)).............................................................. Two-Cycle Demand Transfer (16-bit SRAM to 32-bit DRAM, 32-bit transfer) .......................................... Two-Cycle Demand Transfer (32-bit DRAM to 16-bit SRAM, 32-bit transfer) .......................................... Single Transfer (16-bit SRAM to 32-bit DRAM, 32-bit transfer)................................................................ Single Transfer (8-bit I/O to 32-bit SRAM, 8-bit transfer) ......................................................................... Example of Transfer on Request from Internal Peripheral Hardware....................................................... Transfer End Processing of Channels 0 and 1......................................................................................... DMA Transfer End Output Timing ............................................................................................................ 16- to 32-Bit Data Bus Width (32-bit transfer bus sizing) ......................................................................... 16- to 16-Bit Data Bus Width (32-bit transfer bus sizing) ......................................................................... Block Diagram of UART ........................................................................................................................... Asynchronous Serial Interface Mode Register 00 (ASIM00) .................................................................... Asynchronous Serial Interface Mode Register 01 (ASIM01) .................................................................... Asynchronous Serial Interface Status Register (ASIS0) .......................................................................... Receive Buffer (RXB0, RXB0L)................................................................................................................ Transmit Shift Register (TXS0, TXS0L).................................................................................................... Transmit Data Format of UART ................................................................................................................ Block Diagram of CSI ............................................................................................................................... Clocked Serial Interface Mode Register 0 (CSIM0).................................................................................. Serial I/O Shift Register 0 (SIO0) ............................................................................................................. CSI Transfer Timing ................................................................................................................................. Block Configuration of Baud Rate Generator (BRG) ................................................................................ Baud Rate Generator Compare Register (BRG0) .................................................................................... Baud Rate Generator Prescaler Mode Register (BPRM0) ....................................................................... 15 LIST OF FIGURES (3/3) Figure No. 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 11-1 11-2 11-3 11-4 11-5 11-6 12-1 12-2 12-3 12-4 13-1 13-2 13-3 14-1 Title Page 148 149 149 151 151 152 154 156 157 158 159 160 161 161 162 165 166 166 167 167 168 169 170 171 172 174 179 179 182 Block Configuration of Timer 1 ................................................................................................................. Block Configuration of Timer 4 ................................................................................................................. Timer 1 (TM1) ........................................................................................................................................... Timer 4 (TM4) ........................................................................................................................................... Compare Register (CM4).......................................................................................................................... Capture/Compare Registers (CC10 through CC13) ................................................................................. Timer Unit Mode Register (TUM1)............................................................................................................ Timer Control Register 1 (TMC1).............................................................................................................. Timer Control Register 4 (TMC4).............................................................................................................. Timer Output Control Register (TOC1) ..................................................................................................... Timer Overflow Status Register (TOVS)................................................................................................... Basic Operation of Timer 1 ....................................................................................................................... Example of Capture Operation ................................................................................................................. Basic Operation of Timer 4 ....................................................................................................................... Example of Compare Operation ............................................................................................................... Block Diagram of Port 0............................................................................................................................ Block Diagram of Port 1............................................................................................................................ Block Diagram of Port 2............................................................................................................................ I/O Port Register (PORT).......................................................................................................................... I/O Mode Register (PM) ............................................................................................................................ Port Control Mode Register (PC) .............................................................................................................. Block Diagram of Clock Generation Function........................................................................................... Clock Output Disable Mode ...................................................................................................................... Clock Control Register (CGC) .................................................................................................................. PLL Control Register (PLLCR) ................................................................................................................. Status Transition....................................................................................................................................... STOP Mode Releasing Timing (with NMI signal input)............................................................................. STOP Mode Releasing Timing (with RESET signal input) ....................................................................... Accepting Reset Signal............................................................................................................................. 16 LIST OF TABLES Table No. 2-1 4-1 4-2 4-3 4-4 5-1 5-2 5-3 5-4 5-5 5-6 7-1 9-1 9-2 10-1 11-1 12-1 13-1 13-2 13-3 13-4 14-1 14-2 Title Page 29 37 38 46 48 59 59 74 74 75 77 94 141 144 153 165 169 173 175 176 177 182 183 Status of Each Pin .................................................................................................................................... Interrupt List ............................................................................................................................................. Interrupt List (Maskable interrupts)........................................................................................................... Relation between Priority, Exception Code, Handler Address, and Interrupt Priority............................... Correspondence between Each Bit of Interrupt Control Registers and Interrupt Request Signals .......... 32-Bit Data Bus (xxMWR) ........................................................................................................................ 16-Bit Data Bus (xxMWR) ........................................................................................................................ 32-Bit Data Bus (xxCAS).......................................................................................................................... 16-Bit Data Bus (xxCAS).......................................................................................................................... RAS Active Period .................................................................................................................................... Values of Bus Control Signals during Idle Period..................................................................................... Address Compared by on-page/off-page Judgment................................................................................. Start Condition.......................................................................................................................................... BRG Setting Data ..................................................................................................................................... Capture/Compare Registers..................................................................................................................... Operation in Control Mode ....................................................................................................................... Multiplication Function by PLL Synthesizer.............................................................................................. Operation of Clock Generator in Standby Mode....................................................................................... Operating Status in HALT Mode............................................................................................................... Releasing HALT Mode by Interrupt Request............................................................................................ Operating Status in STOP Mode .............................................................................................................. Status of Output Pin Immediately after Reset .......................................................................................... Initial Value of Each Register after Reset................................................................................................. 17 [MEMO] 18 CHAPTER 1 GENERAL The V831 is a 32-bit RISC microprocessor for embedded control applications, with a high-performance 32-bit V830TM (PD705100) processor core and many peripheral functions such as a DRAM/ROM controller, 4-channel DMA controller, real-time pulse unit, serial interface, and interrupt controller. In addition to high interrupt response speed and optimized pipeline structure, the V831 offers sum-of-products operation instructions, concatenated shift instructions, and high-speed branch instructions to realize multimedia functions, and therefore, can provide high performance in multimedia systems such as internet/intra-net systems, car navigation systems, high-performance television, and color FAXes. 1.1 * Features CPU function V830-compatible instructions Instruction cache Instruction RAM Data cache Data RAM Memory space and I/O space Number of general-purpose registers : 4K bytes : 4K bytes : 4K bytes : 4K bytes : 4G bytes each : 32 bits x 32 Minimum number of instruction execution cycles : 1 cycle * Interrupt/exception function Non-maskable : External input : 1 Maskable : External input : 8 (of which 4 are multiplexed with internal sources) Internal source: 11 types Priority can be specified in 4 groups. * Bus control function Chip select output: 8 blocks (RAS + 7 CS) Memory and I/O space selectable for 4 CS Linear address space of each block: 16M bytes * Wait control function DRAM space I/O space Idle state : Software control of 0 or 1 wait state : Software control of 0 to 15 wait states : 0 to 3 states can be inserted. Other memory spaces : Software control of 0 to 7 wait states 19 CHAPTER 1 GENERAL * Memory access control function DRAM hiper page mode supported Page mode of Page-ROM supported * DMA function 4 channels Maximum number of transfers : 16,777,216 (2 ) Transfer type Transfer mode Programmable wait function : 2-cycle transfer : Single transfer and demand transfer 24 * Serial interface function Asynchronous serial interface (UART) : 1 channel Clocked serial interface (CSI) : 1 channel On-chip dedicated baud rate generator : 1 channel * Timer/counter function 16-bit timer/event counter Timer output 16-bit interval timer : 1 channel :2 : 1 channel 16-bit capture/compare register : 4 * * * * Port function 3 I/O ports Clock generation function PLL clock synthesizer Standby function HALT and STOP modes Debug function Debug-dedicated synchronous serial interface : 1 channel Trace-dedicated interface Trace function * Package 160-pin plastic LQFP (24 x 24 mm) : 1 channel : Branch PC trace and data trace 1.2 Application Fields * Internet/intra-net systems * Car navigation * High-performance television * Color FAX 20 CHAPTER 1 GENERAL 1.3 Ordering Information Part Number Package 160-pin plastic LQFP (fine pitch) (24 x 24 mm) PD705101GM-100-8ED 1.4 Pin Configuration (Top View) * 160-pin plastic LQFP (fine pitch) (24 x 24 mm) PD705101GM-100-8ED VDD D1 D0 LLCAS LUCAS ULCAS UUCAS RAS OE WE A1 GND VDD GND VDD A2 A3 A4 A5 A6 A7 A8 A9 GND VDD A10 A11 GND VDD A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 GND GND D2 D3 D4 D5 D6 D7 D8 VDD GND D9 D10 D11 VDD GND D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 VDD GND D22 D23 D24 VDD GND D25 D26 D27 D28 D29 D30 D31 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VDD CLKOUT TRCDATA0 TRCDATA1 TRCDATA2 TRCDATA3 DDI DCK DMS DDO A22 A23 GND VDD IOWR IORD BCYST READY HLDRQ HLDAK CS1 CS2 GND VDD CS3 CS4 CS5 GND VDD CS6 CS7 INTP10/TO10 INTP12/TO11 INTP11 INTP13 TI TCLR INTP00 INTP01 GND GND LLMWR LUMWR ULMWR UUMWR MRD TXD RXD GND VDD PORT2/SI PORT1/SO PORT0/SCLK VDD_PLL X1 X2 GND_PLL GND VDD GND VDD RESET DRST NMI BT16B GND VDD GND DMAAK0 DMAAK1 DMAAK2 DMAAK3 DMARQ0 DMARQ1 DMARQ2 DMARQ3 TC/REFRQ INTP03 INTP02 VDD 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 21 CHAPTER 1 GENERAL Pin names A1 to A23 BCYST BT16B CLKOUT D0 to D31 DCK DDI DDO : Address Bus : Bus Cycle Start : Boot Bus Size 16 bit : Clock Out RAS READY REFRQ RESET RXD SCLK SI SO TC TCLR TI : Data Bus : Debug Clock : Debug Data Input : Debug Data Output : DMA Acknowledge DMARQ0 to DMARQ3 : DMA Request DMS DRST GND GND_PLL HLDAK HLDRQ : Debug Mode Select : Debug Reset : Ground : PLL Ground : Hold Acknowledge : Hold Request : Interrupt Request From Peripheral IORD IOWR LLCAS LLMWR LUCAS LUMWR MRD : I/O Read : I/O Write : Lower Lower Column Address Strobe : Lower Lower Memory Write : Lower Upper Column Address Strobe : Lower Upper Memory Write : Memory Read TXD ULCAS ULMWR UUCAS UUMWR VDD VDD_PLL WE X1, X2 NMI OE : Non-Maskable Interrupt Request : Output Enable : Port : Row Address Strobe : Ready : Refresh Request : Reset : Receive Data : Serial Clock : Serial Input : Serial Output : Terminal Count : Timer Clear : Timer Input PORT0 to PORT2 CS1 to CS7 : Chip Select DMAAK0 to DMAAK3 TO10, TO11: Timer Output TRCDATA0 to TRCDATA3 : Trace Data : Transmit Data : Upper Lower Column Address Strobe : Upper Lower Memory Write : Upper Upper Column Address Strobe : Upper Upper Memory Write : Power Supply : PLL Power Supply : Write Enable : Crystal Resonator INTP00 to INTP03, INTP10 to INTP13 22 CHAPTER 1 GENERAL 1.5 Internal Block Configuration The internal block configuration of the V831 is as shown below. DCK DMS DDI DDO TRCDATA0 - TRCDATA3 IOWR IORD DCU UUMWR, ULMWR, LUMWR, LLMWR MRD READY BT16B CG BCU BCYST CS1-CS7 A1-A23 SYU V830 core D0-D31 HLDRQ DRST X1 X2 CLKOUT RESET NMI TI, TCLR INTP10/TO10, INTP12/TO11 RPU HLDAK RAS UUCAS, ULCAS, LUCAS, LLCAS INTP11, INTP13 INTP00 - INTP03 ICU WE OE REFRQ/TC PIO PORT0/SCLK PORT1/SO PORT2/SI TXD RXD CSI BRG UART DMAC DMARQ0 - DMARQ3 DMAAK0 - DMAAK3 23 CHAPTER 1 GENERAL 1.6 Internal Units The internal units of the V831 and their functions are as follows: (1) Bus control unit (BCU) Controls the address bus, data bus, and control bus pins. The major functions of BCU are as follows: (a) Bus arbitration Arbitrates the bus mastership among bus masters (CPU, DRAMC, DMAC, and external bus masters). The bus mastership can be changed after completion of the bus cycle under execution, and in an idle state. (b) Wait control Controls eight areas in the 16M-byte space corresponding to a RAS signal and seven chip select signals (CS1 through CS7). Generates chip select signals, controls wait states, and selects the type of bus cycle. (c) DRAM controller Generates RAS and four CAS signals, and controls access to DRAM. The hyper page mode of DRAM is supported and DRAM can be accessed in two types of cycle: normal access (off-page) and hyper page access (on-page). (d) ROM controller Accessing ROM with page access function is supported. The bus cycle immediately before and addresses are compared, and wait states are controlled in the normal access (off-page) and page access (on-page) modes. A page width of 8 bytes to 16 bytes can be supported. (2) Interrupt controller (ICU) Services maskable interrupt requests (INTP00 through INTP03, and INTP10 through INTP13) from internal peripheral hardware and external sources. The priorities of these interrupt requests can be specified in units of four groups, and edge-triggered or level-triggered interrupts can be nested. (3) DMA controller (DMAC) Transfers data between memory and I/O in the place of the CPU. The transfer type is 2-cycle transfer. Two transfer modes, single transfer and demand transfer, are available. (4) Serial interface (UART/CSI/BRG) One asynchronous serial interface (UART) channel and one clocked serial interface (CSI) channel is provided. As the serial clock source, the output of the baud rate generator (BRG) and the bus clock can be selected. (5) Real-time pulse unit (RPU) Provides timer/counter functions. The on-chip 16-bit timer/event counter and 16-bit interval timer can be used to calculate pulse intervals and frequencies, and to output programmable pulses. 24 CHAPTER 1 GENERAL (6) Clock generator (CG) A frequency 3 times higher than that of a resonator connected to the X1 and X2 pins is supplied as the operating clock of the CPU. In addition, a bus clock (with the same cycle as the input clock) is also supplied as the operating clock of the peripheral units. An external clock can be also input instead of connecting a resonator. (7) Port (PIO) Provides port functions. Three I/O ports are available. The pins of these ports can be used as port pins or serial control pin. (8) System control unit (SYU) A circuit that rejects noise on the RESET signal (input)/NMI signal (input) is provided. (9) Debug control unit (DCU) A circuit to realize mapping and trace functions is provided to implement basic debugging functions. 25 [MEMO] 26 CHAPTER 2 PIN FUNCTION 2.1 Pin Function List (1/2) Pin Name I/O 3-state I/O 3-state output Data bus Address bus Column address strobe (most significant byte) Column address strobe (second byte) Column address strobe (third byte) Column address strobe (least significant byte) Row address strobe/chip select Memory write strobe (most significant byte) Memory write strobe (second byte) Memory write strobe (third byte) Memory write strobe (least significant byte) Memory read strobe DRAM write strobe DRAM read strobe I/O read strobe I/O write strobe DRAM refresh request Memory chip select Memory chip select / I/O chip select Bus cycle start Input Specifies bus size on boot Enables end of bus cycle DMA request (CH0 through CH3) Output DMA enable (CH0 through CH3) DMA transfer end Input Output Input Output I/O Input UART data input UART data output CSI data input CSI data output CSI clock I/O Timer 1 count clock input Timer 1 clear, start Output RPU pulse output TC REFRQ PORT2 PORT1 PORT0 INTP10 INTP12 Function Multiplexed Pin D0 - D31 A1 - A23 UUCAS ULCAS LUCAS LLCAS RAS UUMWR ULMWR LUMWR LLMWR MRD WE OE IORD IOWR REFRQ CS1, CS2, CS7 CS3 - CS6 BCYST BT16B READY DMARQ0 - DMARQ3 DMAAK0 - DMAAK3 TC RXD TXD SI SO SCLK TI TCLR TO10 TO11 27 CHAPTER 2 PIN FUNCTION (2/2) Pin Name INTP10 INTP11 INTP12 INTP13 INTP00 - INTP03 HLDRQ HLDAK NMI RESET PORT0 PORT1 PORT2 X1 Connects crystal resonator. (Opened when external clock is input.) Connects crystal resonator or inputs external clock. Bus clock output Debug clock input Debug data input 3-state output Input Debug data output Debug mode select Reset input (debug module) Output Trace data output I/O Output Input Bus request Bus enable Non-maskable interrupt request System reset Port SCLK SO SI TO11 Input I/O Interrupt request Function Multiplexed Pin TO10 X2 CLKOUT DCK DDI DDO DMS DRST TRCDATA0 TRCDATA3 VDD GND VDD_PLL GND_PLL Input Output Input Positive power supply Ground potential Positive power supply for PLL (internal clock generator) Ground potential for PLL (internal clock generator) 28 CHAPTER 2 PIN FUNCTION 2.2 Pin Status Table 2-1 shows the operating status of each pin. Table 2-1. Status of Each Pin Operating Status Pin CLKOUT CS1 - CS7 A1 - A23 D0 - D31 BCYST MRD OE WE LLMWR, LUMWR, ULMWR, UUMWR IORD IOWR HLDAK RAS LLCAS, LUCAS, ULCAS, UUCAS TC/REFRQ Clock output 1 Undefined Hi-Z 1 1 1 1 1 Clock output Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Clock output Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 0 1 Undefined Hi-Z 1 1 1 1 1 Reset Bus Hold HALT Mode STOP Mode 1 1 1 1 1 Hi-Z Hi-Z 0 Hi-Z Hi-Z Note 1 Note 1 Note 1 Note 1 Note 1 0 0 1 1 1 Note 2 Note 3 1 Hi-Z Note 1 0 Note 4 Notes 1. DMA operation can be performed in the HALT mode. 2. The status before the STOP mode is retained if CBR self-refresh is disabled. 3. 1 if CBR self-refresh is disabled. 4. 1 if CBR self-refresh is disabled. If TC is selected, however, TC signal is output. Remark 0 1 : Low-level output : High-level output Hi-Z : high impedance 29 CHAPTER 2 PIN FUNCTION 2.3 Pin Function 2.3.1 Address bus (1) A1 through A23 (Address Bus) *** 3-state output The address bus outputs address signals when the V831 accesses an external main memory or I/O unit. An address space of 2 bytes can be accessed. The address signals change at the rising edge of the bus clock. 2.3.2 Data bus (1) D0 through D31 (Data Bus) *** 3-state I/O The data bus inputs or outputs write data or read data when the V831 accesses an external main memory or I/O unit. These data signals change at the rising edge of the bus clock. 2.3.3 Bus control signals (1) READY (Ready) *** Input This signal extends the bus cycle to match it to the access time of the memory or I/O. It is sampled at the rising edge of the bus clock immediately after the read/write signal. Be sure to observe the setup/hold time of the READY input; otherwise, the operation will not be guaranteed. (2) HLDRQ (Hold Request) *** Input This pin requests the CPU for the bus mastership. It is sampled at the rising edge of the bus clock. (3) HLDAK (Hold Acknowledge) *** Output This is an acknowledge signal in response to the HLDRQ input. When the CPU receives the HLDRQ signal, it asserts the HLDAK signal active. When HLDRQ is deasserted inactive, the CPU deasserts the HLDAK signal inactive, and is granted the bus mastership again. (4) MRD (Memory Read) *** 3-state output This is a strobe signal indicating that the bus cycle under execution is a read cycle of the external memory. It changes in synchronization with the falling of the bus clock. If the Page-ROM cycle continues, however, this signal is always active. It is always inactive in the refresh cycle. (5) LLMWR (Lower Lower Memory Write) *** 3-state output This is a strobe signal for a data write to the external memory. It validates the least significant byte of the data bus. This signal changes in synchronization with the falling of the bus clock. (6) LUMWR (Lower Upper Memory Write) *** 3-state output This is a strobe signal for a data write to the external memory. It validates the third byte of the data bus. This signal changes in synchronization with the falling of the bus clock. (7) ULMWR (Upper Lower Memory Write) *** 3-state output This is a strobe signal for a data write to the external memory. It validates the second byte of the data bus. This signal changes in synchronization with the falling of the bus clock. 24 30 CHAPTER 2 PIN FUNCTION (8) UUMWR (Upper Upper Memory Write) *** 3-state output This is a strobe signal for a data write to the external memory. It validates the most significant byte of the data bus. This signal changes in synchronization with the falling of the bus clock. (9) IORD (I/O Read) *** 3-state output This is a strobe signal indicating that the bus cycle under execution is a read cycle for an external I/O. It changes in synchronization with the falling of the bus clock. (10) IOWR (I/O Write) *** 3-state output This is a strobe signal for a data write to an external I/O. It changes in synchronization with the falling of the bus clock. (11) BT16B (Bout Bus Size 16 bit) *** Input This signal fixes the external data bus width of an area specified by CS7 on initializing the CPU to 16 bits. When this signal is asserted active, a mode supporting a 16-bit data bus system is set. This signal is sampled at the rising of the clock next to the one at which the RESET signal is made high. BT16B can be changed only at reset. If this signal is changed at any other time, the CPU operation is not guaranteed. (12) BCYST (Bus Cycle Start) *** Output This signal indicates the first one cycle of the bus cycle. It is generated at the timing of the CAS cycle when the DRAM is accessed. This signal changes in synchronization with the rising of the bus clock. 2.3.4 System control signals (1) RESET (Reset) *** Input This signal initializes the V831. Be sure to hold the active period of this signal at least for the duration of 25 clocks. The low-level width input to the RESET pin on power application must be wider than the oscillation stabilization time of the resonator. Make sure that the oscillation stabilization time satisfying the specifications of the resonator used elapses. Keep the stabilization time of the PLL to 10 ms or longer. When the RESET signal is input and deasserted inactive, the V831 initializes each signal and internal register, and starts instruction execution from address FFFFFFF0H. (2) X1 and X2 (Crystal Resonator) *** Input Connect a crystal resonator to these pins when the internal clock generator is used. When an external clock is used, input used the clock to the X2 pin. Leave the X1 pin open. (3) CLKOUT (Clock Out) *** Output This pin outputs an internally generated bus clock. (4) CS1, CS2, and CS7 (Chip Select) *** 3-state output These pins output chip select signals to the memory address space. The address block that outputs a signal is fixed for each chip select signal. These signals change in synchronization with the rising of the bus clock. 31 CHAPTER 2 PIN FUNCTION (5) CS3 through CS6 (Chip Select) *** 3-state output These pins output chip select signals to memory address space or I/O address space. To which of these signals are to be output is determined by register setting. The address block that outputs a signal is fixed for each chip select signal. These signals change in synchronization with the rising of the bus clock. 2.3.5 Interrupt control signals (1) INTP10 through INTP13 (Interrupt Request From Peripheral) *** Input These are asynchronous interrupt request signals to the interrupt control unit (ICU). It can be selected whether these signals are triggered by edge or level (high level). When the RPU is used, however, the level trigger cannot be selected. (2) INTP00 through INTP03 (Interrupt Request From Peripheral) *** Input These are asynchronous interrupt request signals for the interrupt control unit (ICU). It can be selected whether these signals are triggered by edge or level (high level). (3) NMI (Non-Maskable Interrupt Request) *** Input This is an interrupt request signal to the CPU which cannot be masked. It is sampled at the rising edge of the clock and rejects noise of 5 clocks or less. The NMI request is accepted at the falling edge of the NMI signal after noise has been rejected. 2.3.6 DRAM control signals (1) REFRQ (Refresh Request) *** 3-state output This is a refresh request signal to the DRAM. It changes in synchronization with the rising of the bus clock. This signal is used to control RAS in the refresh cycle when the number of DRAMs connected is increased by decoding addresses with a external circuit. (2) OE (Output Enable) *** 3-state output This is a read enable signal to the DRAM. It changes in synchronization with the rising of the bus clock. (3) RAS (Row Address Strobe) *** 3-state output This is a raw address strobe signal to the DRAM. Its timing differs in the refresh cycle. This signal changes in synchronization with the rising of the bus clock. (4) LLCAS (Lower Lower Column Address Strobe) *** 3-state output This is a column address strobe signal to the DRAM. It validates the least significant byte of the data bus. Its timing differs in the refresh cycle. This signal changes in synchronization with the falling or rising of the bus clock. (5) LUCAS (Lower Upper Column Address Strobe) *** 3-state output This is a column address strobe signal to the DRAM. It validates the third byte of the data bus. Its timing differs in the refresh cycle. This signal changes in synchronization with the falling or rising of the bus clock. (6) ULCAS (Upper Lower Column Address Strobe) *** 3-state output This is a column address strobe signal to the DRAM. It validates the second byte of the data bus. Its timing differs in the refresh cycle. This signal changes in synchronization with the falling or rising of the bus clock. 32 CHAPTER 2 PIN FUNCTION (7) UUCAS (Upper Upper Column Address Strobe) *** 3-state output This is a column address strobe signal to the DRAM. It validates the most significant byte of the data bus. Its timing differs in the refresh cycle. This signal changes in synchronization with the falling or rising of the bus clock. (8) WE (Write Enable) *** 3-state output This signal indicates that the bus cycle under execution is a write cycle to the DRAM. synchronization with the rising of the bus clock. 2.3.7 DMA control signals (1) DMARQ0 through DMARQ3 (DMA Request) *** Input These are DMA service request signals, and correspond to DMA channels 0 through 3. Their priorities are fixed: DMARQ0 > DMARQ1> DMARQ2 > DMARQ3. The DMARQ0 through DMARQ3 signals are sampled at the rising edge of the bus clock. Keep these signals active until the corresponding DMA requests are accepted. When the DMARQ0 through DMARQ3 signals are not used, deassert these pins inactive (the active levels of these pins can be changed by using a register of the DMAC). (2) DMAAK0 through DMAAK3 (DMA Acknowledge) *** Output These signals indicate that the corresponding DMA service requests are granted. They correspond to DMA channels 0 through 3. These signals are asserted active at the rising edge of the bus clock and remain active during DMA transfer. (3) TC (Terminal Count) *** Output This signal indicates that the DMA transfer by the DMA controller is completed. It is asserted active at the rising edge of the bus clock. Because this signal outputs the logical sum of TC of channels 0 through 3, generate the TC signal of each channel by ANDing the DMAAK0 through DMAAK3 signals with an external circuit. 2.3.8 Real-time pulse control signals (1) TO10 and TO11 (Timer Output) *** Output These signals indicate coincidence between the value of timer 1 (TM1) and the value of the capture/compare register (CC0) of the real-time pulse unit (RPU). The TO10 and TO11 signals are set by detection of coincidence of the CC10 and CC12 registers, and are reset by detection of coincidence of the CC11 and CC13 registers. The output of these signals can be inverted by setting the mode of the RPU. (2) TCLR (Timer Clear) *** Input This is the count clear start signal of TM1 of the RPU. (3) TI (Timer Input) *** Input This is an external clock signal used by TM1 of the RPU. Select whether TM1 of the RPU uses an external clock signal or a clock resulting from dividing the internal bus clock, on initialization. 2.3.9 Serial control signals (1) TXD (Transmit Data) *** Output This is the serial transmit data output pin of UART. The TXD signal changes in synchronization with the internal serial clock. It remains high when no data is transmitted. It changes in 33 CHAPTER 2 PIN FUNCTION (2) RXD (Receive Data) *** Input This is the serial receive data input pin of UART. (3) SCLK (Serial Clock) *** I/O This is the serial clock I/O pin of CSI. Whether this pin is used as an input or output pin is set by a register. (4) SO (Serial Output) *** Output This is the serial transmit data output pin of CSI. It changes in synchronization with the falling of the SCLK signal. This pin goes into a high-impedance state when no data is transmitted. (5) SI (Serial Input) *** Input This is the serial receive data input pin of CSI. The SI signal is sampled at the rising edge of the SCLK signal. 2.3.10 Port control signals (1) PORT0 through PORT2 (Port) *** 3-state I/O These are port signals. The input or output mode of these signals can be selected by a register. 2.3.11 Debug control signals (1) DCK (Debug Clock) *** Input This is a debug clock input pin. The DMS and DDI signals are sampled at the rising edge of the DCK signal, and data is output from the DDO pin at the falling edge of the DCK signal. Keep this signal high when the debug function is not used. (2) DDI (Debug Data Input) *** Input This is a debug data input pin. It is sampled at the rising edge of the DCK signal when the debug serial interface is in the Shift state. Data is input to this pin with the LSB first. Keep this pin high when the debug function is not used. (3) DDO (Debug Data Output) *** 3-state output This is a debug data output pin. It outputs data at the falling edge of the DCK signal with the LSB first when the debug serial interface is in the Shift state. (4) DMS (Debug Mode Select) *** Input This is a debug mode select input pin. The state machine of the debug serial interface changes depending on the level of the DMS signal. The DMS signal is sampled at the rising edge of the DCK signal. Keep this signal high when the debug function is not used. (5) DRST (Debug Reset) *** Input This is a debug reset input pin, and inputs a negative logic signal that initializes the DCU asynchronously. When this signal is made low, the DCU is reset and invalidated. Keep this signal low when the debug function is not used. (6) TRCDATA0 through TRCDATA3 (Trace Data) *** Output These are trace data output pins. They output packet trace data in 4-bit units, starting from the LSB, at the rising edge of the CLKOUT signal. 34 CHAPTER 3 CPU FUNCTION This chapter explains the internal peripheral I/O space and CPU core system registers of the V831. For the instruction set and register configuration, refer to the V830 Family User's Manual-Architecture. For the internal peripheral I/O registers, refer to the description of each register in the function description of the peripheral units. 3.1 Internal Peripheral I/O Space The internal peripheral I/O space is reserved at addresses C0000000H through C00003FFH (1K bytes) of the high-order 1G bytes of the internal I/O area. To access the internal I/Os, use the IN.H/OUT.H instruction (in half-word units) or IN.B/OUT.B instruction (in byte units). When the internal I/O area is accessed, the bus cycle to the external device is not started and the idle state is set. For the status of each pin, refer to 5.6 Idle State. Figure 3-1. Internal Peripheral I/O Map FFFFFFFFH Internal I/O area (1G bytes) Peripheral I/O area C00003FFH Reserved (setting prohibited) C00000F0H C00000EFH CG C00000E0H C00000DFH ICU C00000C0H C00000BFH BRG C00000B0H C00000AFH CSI C00000A0H C000009FH UART C0000090H C000008FH RPU C0000070H C000006FH DMA C0000030H C000002FH BCU C0000020H C000001FH WCU C0000010H C000000FH PIO C0000000H C0000000H BFFFFFFFH External I/O area (1G bytes) 80000000H 7FFFFFFFH External I/O area (1G bytes) 40000000H 3FFFFFFFH External I/O area (1G bytes) 00000000H 35 CHAPTER 3 CPU FUNCTION 3.1.1 Notes Note the following points when using the internal peripheral I/O space. * Only the low-order 10 bits of a 32-bit address are used to decode a register address in terms of hardware, and an area of 1K bytes is used for register allocation. * The low-order bit (A0) of an address is not decoded. If a register at an odd address (address 2n+1) is accessed in byte units, therefore, a register at an even address (address 2n) is accessed by the hardware. * The V831 does not have a register that can be accessed in word units. If an internal peripheral I/O register is accessed in word units, it is forcibly accessed in half-word units. * If a register that can be accessed in byte units is accessed in half-word units, the high-order 8 bits are undefined when the register is read. When data is written to the register, the low-order 8 bits are written. * Addresses not allocated to registers are reserved for future expansion. If these addresses are accessed, the operation is undefined and not guaranteed. 3.2 CPU Core System Registers With the V831, the processor ID register (PIR) is changed. PIR is a register that only identifies the CPU type number, and its contents are fixed to 00008301H (this register can be only read in 32-bit units). For the initial value of each register after reset, refer to Table 14-2. Initial Value of Each Register after Reset. 36 CHAPTER 4 INTERRUPT/EXCEPTION PROCESSING FUNCTION 4.1 Interrupt/Exception Processing The V831 has a dedicated interrupt controller (ICU) that can process a total of 15 interrupt requests. An interrupt is an event that takes place independently of program execution. On the other hand, an exception is an event that takes place depending on program execution. In general, interrupts are processed prior to exceptions. In the V831, each interrupt request from on-chip peripheral function units and external units can be processed. Exception processing can be started by an instruction (TRAP instruction) or by occurrence of an exception (such as an illegal instruction code (except address trap exception)). The cause of an exception can be identified by an exception code stored to ECR (Exception Cause Register). Four levels of priorities can be specified in software for interrupt requests. An interrupt servicing is started at least six bus clocks after the request has been issued. Three bus clocks of these six bus clocks are used to reject noise. An internal interrupt is started at least 3 bus clocks after the request has been issued. 4.1.1 Interrupt/exception processing types The interrupts/exceptions of the V831 can be classified into the following four types: * Non-maskable interrupt: 1 source * Maskable interrupt * Software exception * Exception trap : 15 sources : 32 sources : 4 sources Table 4-1. Interrupt List Source of Interrupt/Exception Name Reset Non-maskable Software exception Interrupt Interrupt Exception RESET NMI TRAP 1nH TRAP 0nH Exception trap Exception NMI FAULT I-OPC DIV0 Note 1 Type Classification Exception Code (ECR) FFF0H FFD0H FFBnH FFAnH Note 4 Not affected FF90H FF80H Handler Address FFFFFFF0H FFFFFFD0H FFFFFFB0H FFFFFFA0H FFFFFFD0H FFFFFFE0H FFFFFF90H FFFFFF80H Restore PC Note 2 Cause Reset input NMI input TRAP instruction TRAP instruction Dual exception Fatal exception Illegal instruction code Zero division Undefined next PC next PC Note 3 current PC Notes 1. Handler names used in development tools or software. 2. The PC value saved to EIPC/FEPC/DPC when interrupt/exception processing is started. 3. Execution of all instructions cannot be stopped by an interrupt. 4. The exception code of an exception causing a dual exception. Remark n = 0H to FH 37 CHAPTER 4 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 4-2. Interrupt List (Maskable interrupts) InGroup Priority 3 2 1 0 GR2 3 2 1 0 GR1 3 2 Cause of Interrupt Name RESERVED Reserved INTOV1 INTSER INTP03 INTSR INTST INTCSI INTP02 INTDMA INTP10/ INTCC10 INTP11/ INTCC11 INTP01 INTCM4 INTP12/ INTCC12 INTP13/ INTCC13 INTP00 Timer 1 overflow UART receive error INTP03 pin input UART receive end UART transmit end CSI transmit/receive end INTP02 pin input DMA transfer end INTP10 pin input/ coincidence of CC10 INTP11 pin input/ coincidence of CC11 INTP01 pin input Coincidence of CM4 INTP12 pin input/ coincidence of CC12 INTP13 pin input/ coincidence of CC13 INTP00 pin input Cause Unit RPU UART External UART UART CSI External DMAC External/ RPU External/ RPU External RPU External/ RPU External/ RPU External Handler Address Note 3 Type Classification Group Exception Code FEF0H Restore Note 1 HCCW.IHA=0 HCCW.IHA=1 PC Mask- Interrupt GR3 able FFFFFEF0H FE0000F0H next Note 2 PC FEE0H FFFFFEE0H FE0000E0H FED0H FFFFFED0H FE0000D0H FEC0H FFFFFEC0H FE0000C0H FEB0H FFFFFEB0H FE0000B0H FEA0H FFFFFEA0H FE0000A0H FE90H FE80H FE70H FE60H FFFFFE90H FE000090H FFFFFE80H FE000080H FFFFFE70H FE000070H FFFFFE60H FE000060H 1 FE50H FFFFFE50H FE000050H 0 GR0 3 2 FE40H FE30H FE20H FFFFFE40H FE000040H FFFFFE30H FE000030H FFFFFE20H FE000020H 1 FE10H FFFFFE10H FE000010H 0 FE00H FFFFFE00H FE000000H Notes 1. The PC value saved to EIPC when interrupt servicing is started. 2. Execution of all instructions cannot be stopped by an interrupt. 3. FFFFFEn0H can be selected as a handler address when HCCW.IHA = 0, and FE0000n0H can be selected when HCCW.IHA = 1 (N = 0H to FH). Caution The exception codes and handler addresses of the maskable interrupts shown above are the values if the default priority is used. If the priority is changed, refer to Table 4-3 Relation between Priority, Exception Code, Handler Address, and Interrupt Priority. 38 CHAPTER 4 INTERRUPT/EXCEPTION PROCESSING FUNCTION 4.2 Non-Maskable Interrupt A non-maskable interrupt is unconditionally accepted even when interrupts are disabled. It takes precedence over all the other interrupts and is not controlled by the priority. The non-maskable interrupt request is issued by the NMI pin. 4.2.1 Servicing non-maskable interrupt If a non-maskable interrupt occurs because the NMI signal is input, the processing shown in Figure 4-1 is performed, and control is transferred to the handler routine. FEPC and FEPSW are used as status saving registers. The NMI signal that is input while the non-maskable interrupt is processed (PSW.NP = 1) is kept pending by the CPU. In this case, if PSW.NP is cleared to 0 by using the RETI or LDSR instruction, new non-maskable interrupt servicing is started by the pending non-maskable interrupt request. Figure 4-1. Processing Flow of Non-Maskable Interrupt NMI input Non-maskable interrupt request PSW.NP CPU processing 0 FEPC Restore PC FEPSW PSW ECR.FECC Exception code PSW.NP 1 PSW.ID 1 PC Handler address 1 Interrupt request pending Interrupt servicing 39 CHAPTER 4 INTERRUPT/EXCEPTION PROCESSING FUNCTION 4.3 Maskable Interrupts Maskable interrupt requests can be masked by control registers. The V831 has 15 maskable interrupt sources. If two or more maskable interrupts occur at the same time, they are accepted according to the default priority determined in advance by the ICU. In addition to the default priority, four levels of priorities can be specified in software (priority in a group is fixed). A maskable interrupt is masked by the logical sum of the NP, EP, and ID bits of the PSW. If interrupt level n that is passed to the CPU is lower than the interrupt enable level of the PSW (specified by bits I0 through I3 of the PSW), the interrupt is not accepted. Therefore, the highest interrupt level (n = 15) cannot be disabled by the interrupt enable level. When an interrupt request is accepted, the other interrupts are disabled (PSW.ID = 1); therefore, no more maskable interrupts can be accepted. The accepted interrupt level n plus 1 (n+1) is set to the I0 through I3 bits of the PSW. To enable nesting of interrupts, first save the EIPC and EIPSW to the memory or register, and then enable the interrupts (PSW.ID = 0, EP = 0). Execute the RETI instruction after disabling the interrupts (PSW.ID = 1), and restore EIPC and EIPSW to the original values. 4.3.1 Maskable interrupt servicing format If a maskable interrupt occurs due to input of an interrupt request signal (INT), the processing shown in Figure 4-2 is performed, and control is transferred to the handler routine. EIPC and EIPSW are used as status saving registers. The INT input masked by the ICU and INT input that takes place while another interrupt is serviced (PSW.NP = 1 or PSW.ID = 1) is kept pending by the ICU. In this case, if the interrupt is unmasked, or if the PSW.NP and PSW.ID are cleared to 0 by using the RETI or LDSR instruction, new maskable interrupt servicing is started by the pending INT input. 40 CHAPTER 4 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 4-2. Maskable Interrupt Servicing Flow INT input REQxx = 1? 1 ICU accept MSKxx = 0? 0 Priority higher than other INT? 0 1 Level trigger Edge trigger No Edge trigger Level trigger Yes Maskable interrupt request Interrupt request pending Interrupt request ignored PSW.NP 0 PSW.EP 0 PSW.ID 0 INT level 1 1 1 CPU processing < Interrupt enable level Interrupt enable level EIPC Restore PC EIPSW PSW ECR.EICC Exception code PSW.EP 1 PSW.ID 1 PSW.I0 - I3 Interrupt level + 1 (15 when PSW.I = 15) PC Handler address Interrupt request ignored Interrupt servicing 41 CHAPTER 4 INTERRUPT/EXCEPTION PROCESSING FUNCTION 4.3.2 Priority of maskable interrupt The V831 can nest interrupts by accepting an interrupt while it is servicing another interrupt. Nesting can be controlled by the priority. Priority control is implemented by the default priority or by software, using the interrupt group priority register. When two or more interrupts occur at the same time, the interrupts are serviced according to the priority (default priority) allocated in advance to each group of interrupt requests (with one group consisting of four interrupts) (refer to Table 4-2. Interrupt List (Maskable Interrupts)). The priority is also controlled by software by classifying the interrupt requests into four groups, using the interrupt group priority control register. In each group, the priorities of the interrupts are fixed. When an interrupt is accepted, the ID flag and EP flag of the PSW are automatically set. To perform nesting of interrupts, therefore, enable interrupts (PSW.ID = 0, PSW.EP = 0) in the interrupt servicing program. (Service program of maskable interrupt or exception) * * * Saves EIPC to memory or register. Saves EIPSW to memory or register. Enables accepting interrupt (PSW.ID = 0, PSW.EP = 0). ... ... ... * * * * Disables accepting interrupt (PSW.ID = 1, PSW.EP = 1). Restores saved value to EIPSW. Restores saved value to EIPC. Executes RETI instruction. Interrupt such as INT input is accepted. 42 CHAPTER 4 INTERRUPT/EXCEPTION PROCESSING FUNCTION 4.4 Exception Processing If an exception occurs, the following processing is performed and control is transferred to the handler routine. Figure 4-3. Exception Processing Flow Exception occurs PSW.NP 0 PSW.EP 0 EIPC Restore PC EIPSW PSW ECR.EICC Exception code PSW.EP 1 PSW.ID 1 PC Handler address 1 Fatal exception 1 Dual exception FEPC Restore PC FEPSW PSW ECR.FECC Exception code PSW.NP 1 PSW.ID 1 PC Handler address DPC Restore PC DPSW PSW PSW.NP 1 PSW.DP 1 PSW.EP 1 PSW.ID 1 PC Handler address Interrupt servicing Interrupt servicing Interrupt servicing 43 CHAPTER 4 INTERRUPT/EXCEPTION PROCESSING FUNCTION 4.5 Restoring from Exception/Interrupt 4.5.1 Restoring from exception/interrupt Program execution is restored from an exception or interrupt event other than a fatal exception by using the RETI instruction. Figure 4-4. Flow of Restoration from Exception/Interrupt RETI instruction PSW.NP 0 PC EIPC PSW EIPSW 1 PC FEPC PSW FEPSW Jumps to PC Jumps to PC 4.5.2 Restoring from fatal exception routine Program execution is restored from fatal exception processing by using the BRKRET instruction. Figure 4-5. Flow of Restoration from Fatal Exception Routine BRKRET instruction PC DPC PSW DPSW Jumps to PC 44 CHAPTER 4 INTERRUPT/EXCEPTION PROCESSING FUNCTION 4.6 Interrupt Control Registers It can be selected whether an interrupt is triggered by edge or level. All the interrupts caused by the internal units of the V831 are triggered by edge. For an explanation of how to specify level trigger or edge trigger, refer to 4.6.5 ICU mode register (IMOD). 4.6.1 Interrupt group priority register (IGP) The interrupt group priority register (IGP) specifies the priority between interrupt groups. Specify or change the priority with the interrupts masked. Table 4-3 shows the relation of the handler addresses. Figure 4-6. Interrupt Group Priority Register (IGP) Address: C00000C0H IGP 7 PR3 6 5 PR2 4 3 PR1 2 1 PR0 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W Bit 7-0 Bit Name PR3 - PR0 Group Priority Description Specifies priority of interrupt group n (PRn) of four interrupt groups (n = 0 to 3). 0 is the lowest priority, while 3 is the highest. PRn 0 0 1 1 0 1 0 1 0 (Lowest) 1 2 3 (Highest) Priority Caution Do not use the same priority between groups; otherwise, the operation is not guaranteed. 45 CHAPTER 4 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 4-3. Relation between Priority, Exception Code, Handler Address, and Interrupt Priority Handler Address Handler Name Note Priority of Each Group (setting of IGP) 3 (highest) Priority in Group (Fixed) 3 (highest) 2 1 0 (lowest) Exception Code FEF0H FEE0H FED0H FEC0H FEB0H FEA0H FE90H FE80H FE70H FE60H FE50H FE40H FE30H FE20H FE10H FE00H Interrupt Priority Highest HCCW. IHA = 0 HCCW. IHA = 1 HCCW. IHA = 0 HCCW. IHA = 1 FFFFFEF0H FFFFFEE0H FFFFFED0H FFFFFEC0H FFFFFEB0H FFFFFEA0H FFFFFE90H FFFFFE80H FFFFFE70H FFFFFE60H FFFFFE50H FFFFFE40H FFFFFE30H FFFFFE20H FFFFFE10H FFFFFE00H FE0000F0H FE0000E0H FE0000D0H FE0000C0H FE0000B0H FE0000A0H FE000090H FE000080H FE000070H FE000060H FE000050H FE000040H FE000030H FE000020H FE000010H FE000000H INT0F INT0E INT0D INT0C INT0B INT0A INT09 INT08 INT07 INT06 INT05 INT04 INT03 INT02 INT01 INT00 INT1F INT1E INT1D INT1C INT1B INT1A INT19 INT18 INT17 INT16 INT15 INT14 INT13 INT12 INT11 INT10 2 3 2 1 0 1 3 2 1 0 0 (lowest) 3 2 1 0 Lowest Note Handler names used in development tools or softwarwe. 4.6.2 Interrupt clear register (ICR) This register clears interrupt requests. Figure 4-7. Interrupt Clear Register (ICR) Address: C00000C2H 15 ICR 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLR14 CLR13 CLR12 CLR11 CLR10 CLR9 CLR8 CLR7 CLR6 CLR5 CLR4 CLR3 CLR2 CLR1 CLR0 Initial value: R/W: 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Bit 14 - 0 Bit Name CLR14 - CLR0 Clear Interrupt Request Description Clears the corresponding interrupt request (REQn bit of IRR register) when this register is manipulated. An interrupt request in the level mode cannot be cleared by these bits, and these bits can be only written. These bits are 0 when they are read, regardless of the ICR register. 0: Performs nothing. 1: Clears REQn bit of IRR register (n = 0 to 14). 46 CHAPTER 4 INTERRUPT/EXCEPTION PROCESSING FUNCTION 4.6.3 Interrupt request register (IRR) This register holds interrupt requests. Figure 4-8. Interrupt Request Register (IRR) Address: C00000C4H 15 IRR 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REQ14 REQ13 REQ12 REQ11 REQ10 REQ9 REQ8 REQ7 REQ6 REQ5 REQ4 REQ3 REQ2 REQ1 REQ0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 14 - 0 Bit Name REQ14 - REQ0 Interrupt Request Description These bits are set when the corresponding interrupt requests are issued. They are not affected by the mask register. If an interrupt is triggered by edge, these bits are reset by manipulation of the ICR register. The IRR register can be read only and cannot be written. 0: No interrupt request is generated. 1: Interrupt request is generated. 4.6.4 Interrupt request mask register (IMR) This register masks interrupt requests. Figure 4-9. Interrupt Request Mask Register (IMR) Address: C00000C6H 15 IMR 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSK14 MSK13 MSK12 MSK11 MSK10 MSK9 MSK8 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 Initial value: R/W: 1 R 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bit 14 - 0 Bit Name MSK14 - MSK0 Mask Interrupt Request Description These bits mask the corresponding interrupt requests. Mask the interrupts when they are not occurring. 0: Interrupt not masked. 1: Masks interrupt. 47 CHAPTER 4 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 4-4. Correspondence between Each Bit of Interrupt Control Registers and Interrupt Request Signals Bits of ICR Register CLR14 CLR13 CLR12 CLR11 CLR10 CLR9 CLR8 CLR7 CLR6 CLR5 CLR4 CLR3 CLR2 CLR1 CLR0 Bits of IRR Register REQ14 REQ13 REQ12 REQ11 REQ10 REQ9 REQ8 REQ7 REQ6 REQ5 REQ4 REQ3 REQ2 REQ1 REQ0 Bits of IMR Register MSK14 MSK13 MSK12 MSK11 MSK10 MSK9 MSK8 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 Interrupt Request Signals INTOV1 INTSER INTP03 INTSR INTST INTCSI INTP02 INTDMA INTP10/INTCC10 INTP11/INTCC11 INTP01 INTCM4 INTP12/INTCC12 INTP13/INTCC13 INTP00 Caution These bits are independent of the priority of each interrupt group and correspond to fixed interrupts. 4.6.5 ICU mode register (IMOD) This register specifies the trigger mode of the interrupt requests input from external pins (INTP00 through INTP03 and INTP10 through INTP13). Two trigger modes, level trigger and edge trigger, can be used. (1) Level trigger In this trigger mode, the external interrupt request is sampled at each clock. When an interrupt request is issued, hold the active level of the interrupt (high level) until the interrupt handler of the CPU recognizes the interrupt request. If the interrupt request is cleared before it is recognized, malfunctioning such as an undefined branch destination vector occurs. The interrupt request register (IRR) cannot be cleared by the interrupt clear register (ICR). (2) Edge trigger In this trigger mode, the external interrupt is sampled at the rising edge of clock. If the interrupt request signal changes at the edge specified by the IMOD register at the rising edge of the clock, the interrupt request is accepted. The interrupt request is counted only once even when it is input repeatedly. Because the internal interrupt is also input at an edge, clear the corresponding bit of the interrupt request register (IRR) in the interrupt servicing routine. Caution Keep the interrupt request level for the duration of at least 3 bus clocks in the edge trigger mode because of limitations of the internal edge detection circuit. 48 CHAPTER 4 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 4-10. ICU Mode Register (IMOD) Address: C00000C8H 15 IMOD 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ITM13 ITM12 ITM11 ITM10 ITM03 ITM02 ITM01 ITM00 Initial value: R/W: 1 R/W 0 1 R/W 0 1 R/W 0 1 R/W 0 1 R/W 0 1 R/W 0 1 R/W 0 1 R/W 0 Bit 15 - 8 Bit Name ITM13 - ITM10 Interrupt Trigger Mode1 Description These bits specify the trigger mode of the INTP1n pin. Change the setting of the trigger mode only when the interrupt request is not going to occur (n = 0 to 3). The INTP1n pin is multiplexed with the interrupt for capture mode of timer 1 of the RPU. Therefore, the valid trigger mode differs as follows depending on the setting of the TUM1 register of the RPU. (1) When CMS1n = 1 and IMS1n = 1 is set to TUM1 register (n = 0 to 3) ITM1n 0 0 1 1 0 1 0 1 Trigger mode Level trigger (high active) Reserved (setting prohibited) Rising edge trigger Reserved (setting prohibited) (2) When CMS1n = 1 and IMS1n = 0 is set to TUM1 register (n = 0 to 3) ITM1n 0 0 1 1 0 1 0 1 Trigger mode Reserved (setting prohibited) Reserved (setting prohibited) Rising edge trigger Reserved (setting prohibited) (3) When CMS1n = 0 is set to TUM1 register (n = 0 to 3) ITM1n 0 0 1 1 0 1 0 1 Trigger mode Reserved (setting prohibited) Reserved (setting prohibited) Rising edge trigger Both rising and falling edge triggers Caution Do not change the setting of ITM13 through ITM10 while the timer 1 of RPU is operating. 7-0 ITM03 - ITM00 Interrupt Trigger Mode0 These bits set the trigger mode of the INTP0n pin. Change the setting of the trigger mode only when the interrupt request is not going to occur (n = 0 to 3). ITM0n 0 0 1 1 0 1 0 1 Trigger mode Level trigger (high active) Reserved (setting prohibited) Rising edge trigger Reserved (setting prohibited) 49 CHAPTER 4 INTERRUPT/EXCEPTION PROCESSING FUNCTION 4.7 Interrupt Requests by External Input Pins An interrupt request is input by external input pin INTP0n or INTP1n. To input an interrupt request from an external input pin, set the following registers: * Interrupt request mask register (IMR) (Refer to 4.6.4.) * ICU mode register (IMOD) (Refer to 4.6.5.) * Timer unit mode register (TUMI) (Refer to 10.3.1.) (1) When using INTP0n pin * Set the trigger mode by using the ICU mode register (IMOD). * Unmask "interrupt request" by using the interrupt request mask register. (2) When using INTP1n pin as external input interrupt pin * Set the trigger mode by using the ICU mode register (IMOD). * Unmask the interrupt request by using the interrupt request mask register. * Set the IMS bit of the control register and timer unit mode register (TUM1) of timer 1 to 1. (External input signals are used as interrupt request signals.) INTP1n is multiplexed with the capture function of timer 1. To use the capture function of timer 1, the INTP1n pin corresponding to the capture register to be used inputs a capture trigger (capture interrupt). The request signal and vector address of INTP1n are multiplexed with the coincidence interrupt INTCC1n of the compare register. When using the coincidence interrupt of the compare register, therefore, the INTP1n pin function cannot be used. For details, refer to CHAPTER 10 TIMER/COUNTER FUNCTION. Remark n = 0 to 3 50 CHAPTER 5 BUS CONTROL FUNCTION The BCU of the V831 can directly connect to EDO DRAM (Extended Data Output DRAM), Page-ROM, SRAM (ROM), or I/O. To access EDO DRAM, four xxCAS signals, and the RAS, OE, and WE signals are used in addition to the address and data buses. Addresses are output to DRAM from address pins by multiplexing row and column addresses. To access Page-ROM or SRAM (ROM), four xxMWR signals, and the MRD and CS signals are used in addition to the address and data buses. To access an I/O, address bus, data bus, IOWR, IORD, and CS signals are used. When accessing Page-ROM, SRAM (ROM), or I/O, wait control can be also performed by using the READY signal. For access arbitration with an external bus master, the HLDRQ and HLDAK signals are used. Remarks 1. xxCAS : UUCAS, ULCAS, LUCAS, LLCAS 2. xxMWR : UUMWR, ULMWR, LUMWR, LLMWR 5.1 Features * Directly connects to EDO DRAM, Page-ROM, SRAM (ROM), or I/O * CAS access with 1 bus clock minimum * DRAM byte access control with four CAS signals * Wait control by READY signal 5.2 External I/O Cycle The I/O cycle is executed if block 3 to 6 of the I/O space is accessed by the IN/OUT instructions and if the I/O cycle is selected by the BCTC register. The I/O cycle is a single cycle only, and the basic cycle is a 2-bus clock cycle of Ta and Ts states (refer to Figure 5-1). The Ta state starts output of control signals to an external device. An address is output at the rising edge of the bus clock, and the CS signal is asserted active. The BCYST signal is active in the Ta state period (1 bus clock). When the external device is read or written, the IORD or IOWR signal is asserted active at the falling edge of the bus clock. Write data is output at the rising edge of the bus clock. The Ts state reads or writes data to an external device. During read, the data is sampled at the falling edge of the bus clock. Output of write data continues during the Ts state period. The READY signal is sampled at the rising edge of the bus clock of the Ts state. When the READY signal is active, the IORD or IOWR signal deasserted inactive, and the read/write cycle is completed. If the READY signal is inactive, the Ts state is executed once again. After the I/O read cycle is executed by the CPU, a Ti state is forcibly inserted for the duration of one bus clock. The wait states can be also controlled by using the PWC0/PWC1 register, in addition to the READY signal. Because the number of wait states set by the PWC0/PWC1 register is ORed with the number of wait states input by the READY signal, whichever number of wait states is greater is inserted. 51 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-1. External I/O Cycle (32-bit bus mode) Ta CLKOUT (output) Ts Ti Ta Ts Ts Ts Ti BCYST (output) A2 - A23 (output) CSn (output) IORD (output) Read D0 - D31 (input) IOWR (output) Write D0 - D31 (output) READY (input) Remarks 1. 2. 3. n = 3 to 6 The dotted lines indicate the high-impedance state. The arrows indicate sampling timing. 5.2.1 Byte access control Because only the IOWR signal is available as an I/O write strobe signal, accessing the external I/O cannot be controlled in byte units. Therefore, connect the I/O in word units when the data bus width is 32 bits, or in half word units when the data bus width is 16 bits. The level of A1 is changed when the external I/O is accessed in half-word units via the 32-bit data bus. 52 CHAPTER 5 BUS CONTROL FUNCTION 5.3 SRAM (ROM) Cycle The SRAM (ROM) cycle is executed when block 1 to 7 of the memory space is accessed and when the SRAM (ROM) cycle is selected by the BCTC register. The SRAM (ROM) cycle is classified into the following types by the length of data accessed successively and data bus width. (1) Classification by length of data successively accessed * Single cycle (access unit: 4/2/1 byte) * SRAM (ROM) access by ST instruction execution * SRAM (ROM) access by execution of LD instruction to uncacheable area or instruction fetch * SRAM (ROM) access by 2-cycle transfer of DMA * Burst cycle (access unit: 16 bytes) * SRAM (ROM) access by refilling of instruction/data cache * SRAM (ROM) access by execution of instruction that transfers blocks with internal RAM (2) Classification by data bus width * The data bus width is set by the BWn bit of the DBC register (n = 1 to 6). * * When BWn bit = 1: 16-bit bus mode When BWn bit = 0: 32-bit bus mode Figure 5-2. Example of Connection of 16M ROM (1M x 16) (in 32-bit bus mode) V831 A2 - A21 D0 - D15 D16 - D31 MRD CSn OE CE 1M x 16 (Page) ROM A0 - A19 O0 - O15 WORD/BYTE 1M x 16 (Page) ROM A0 - A19 O0 - O15 WORD/BYTE OE CE 53 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-3. Example of Connection of 1M SRAM (128K x 8) (in 32-bit bus mode) V831 A2 - A18 D0 - D7 CSn MRD LLMWR 128K x 8 SRAM A0 - A16 I/O1 - I/O8 CS OE WE 128K x 8 SRAM A0 - A16 D8 - D15 I/O1 - I/O8 CS OE LUMWR WE 128K x 8 SRAM A0 - A16 D16 - D23 I/O1 - I/O8 CS OE ULMWR WE 128K x 8 SRAM A0 - A16 D24 - D31 I/O1 - I/O8 CS OE UUMWR WE 54 CHAPTER 5 BUS CONTROL FUNCTION 5.3.1 SRAM (ROM) single cycle The SRAM (ROM) cycle is started when a block setting the SRAM (ROM) cycle is accessed by executing the ST instruction or uncacheable LD instruction, or by instruction fetch or DMA2 cycle transfer. The basic cycle is a 2-bus clock cycle of Ta and Ts states (refer to Figure 5-4). The Ta state starts output of control signals to an external device. An address is output at the rising edge of the bus clock, and the CS signal is asserted active. The BCYST signal is active in the Ta state period (1 bus clock). When the external device is read or written, the MRD or xxMWR signal is asserted active at the falling edge of the bus clock. Write data is output at the rising edge of the bus clock. The Ts state reads or writes data of an external device. During read, the data is sampled at the falling edge of the bus clock. Output of write data continues during the Ts state period. The READY signal is sampled at the rising edge of the bus clock of the Ts state. When the READY signal is asserted active, the cycle is completed with the MRD or xxMWR signal deasserted inactive. If the READY signal is deasserted inactive, the Ts state is executed once again. After the SRAM (ROM) read cycle executed by the CPU, a Ti state is forcibly inserted for the duration of one bus clock. The wait states can be also controlled by using the PWC0/PWC1 register, in addition to the READY pin (refer to Figure 5-4). Because the number of wait states set by the PWC0/PWC1 register is ORed with the number of wait states input by the READY signal, whichever number of wait states is greater is inserted. Remark xxMWR: UUMWR, ULMWR, LUMWR, LLMWR 55 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-4. SRAM (ROM) Single Cycle (32-bit bus mode) Ta CLKOUT (output) Ts Ti Ta Ts Ts Ts Ti BCYST (output) A2 - A23 (output) CSn (output) MRD (output) Read D0 - D31 (input) xxMWR (output) Write D0 - D31 (output) READY (input) Remarks 1. 2. 3. 4. n = 1 to 7 xxMWR: LLMWR, LUMWR, ULMWR, UUMWR The dotted lines indicate the high-impedance state. The arrows indicate sampling timing. 56 CHAPTER 5 BUS CONTROL FUNCTION 5.3.2 SRAM (ROM) burst cycle The SRAM (ROM) burst cycle is started when block setting the SRAM (ROM) cycle is accessed by refilling the instruction/data cache or executing an instruction that transfers blocks with the internal RAM. The basic access is a 2-bus clock access. In the 32-bit bus mode, access is made four times in a row in one burst cycle (refer to Figure 55). The timing of the SRAM (ROM) control signals for one access is the same as that in the single cycle, except the MRD signal. The MRD signal remains active during the period of the burst cycle in synchronization with the rising of the bus clock. The BCYST signal remains active during the period of Ta to Ta4 states for each access. The READY signal is sampled at the rising edge of the bus clock of the Ts state. The wait states can be also controlled by using the PWC0/PWC1 register, in addition to the READY pin. Because the number of wait states set by the PWC0/PWC1 register is ORed with the number of wait states input by the READY signal, whichever number of wait states is greater is inserted. 57 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-5. SRAM (ROM) Burst Cycle Ta CLKOUT (output) Tb1 Ta2 Tb2 Ta3 Tb3 Ta4 Ts Ti BCYST (output) A2 - A23 (output) A1 A2 A3 A4 CSn (output) MRD (output) Read D0 - D31 (input) 1 2 3 4 xxMWR (output) Write D0 - D31 (output) 1 2 3 4 READY (input) Remarks 1. 2. 3. 4. n = 1 to 7 xxMWR: LLMWR, LUMWR, ULMWR, UUMWR The dotted lines indicate the high-impedance state. The arrows indicate sampling timing. 58 CHAPTER 5 BUS CONTROL FUNCTION 5.3.3 Byte access control Byte access is controlled by using four xxMWR signals (UUMWR, ULMWR, LUMWR, and LLMWR). When the data bus width is 32 bits, the four xxMWR signals are used; when it is 16 bits, two xxMWR signals (LUMWR and LLMWR) are used. The relation between the xxMWR signals and access address is shown below. xxMWR) Table 5-1. 32-Bit Data Bus (xx xx Address Data Size A1 Byte 0 0 1 1 Half word (16 bits) 0 1 Word (32 bits) 0 A0 0 1 0 1 0 0 0 UUMWR 1 1 1 0 1 0 0 1 1 0 1 1 0 0 xxMWR ULMWR LUMWR 1 0 1 1 0 1 0 LLMWR 0 1 1 1 0 1 0 Remarks 1: High-level output 0: Low-level output xxMWR) Table 5-2. 16-Bit Data Bus (xx xx Address Data Size A0 Byte 0 1 Half word (16 bits) Word (32 bits) First Second 0 0 0 UUMWR 1 1 1 1 1 1 1 1 1 1 xxMWR ULMWR LUMWR 1 0 0 0 0 LLMWR 0 1 0 0 0 Remarks 1: High-level output 0: Low-level output 59 CHAPTER 5 BUS CONTROL FUNCTION 5.4 Page-ROM Cycle When the block 7 area of the memory space is accessed with the Page-ROM cycle selected by the CT7 bit of the BCTC register, the Page-ROM cycle is executed. The Page-ROM cycle is classified into the following types by the length of data accessed successively and the data bus width. (1) Classification by length of data accessed successively * Single cycle (access unit: 4/2/1 byte) * Page-ROM access by execution of LD instruction to uncacheable area or instruction fetch * Page-ROM access by 2-cycle transfer of DMA * Burst cycle (access unit: 16 bytes) * * Page-ROM access by refilling instruction cache Page-ROM access by execution of instruction that transfers blocks with internal RAM (2) Classification by data bus width * The data bus width is set by using the BT16B pin. Access is made four times in a row in the burst cycle and in the 32-bit bus mode. In the 16-bit bus mode, access is made eight times in a row. * When BT16B pin = 1: 16-bit bus mode * When BT16B pin = 0: 32-bit bus mode 5.4.1 Page-ROM single cycle This cycle is started to access block 7 for which the Page-ROM cycle is selected by execution of the uncacheable LD instruction, instruction fetch, or DMA2 cycle transfer. Wait states can be controlled by using the READY pin or an internal register. To control wait states, the WS7 bit of he PWC1 register is used. The bus timing is the same as the SRAM (ROM) single cycle. 5.4.2 Page-ROM burst cycle This cycle is started to access block 7 for which the Page-ROM cycle is selected by refilling the instruction cache or executing an instruction that transfers blocks with the internal RAM. The bus timing is the same as the SRAM (ROM) burst cycle, but the number of wait states is set differently. If the PS bit of the PRC register is 0 (page size is 16 bytes) in the 32-bit bus mode or 16-bit bus mode, the normal access (off-page) is executed as the first access, and on-page access is executed from the second access and onward. The basic cycle of one access is 2-bus clock cycles. (Refer to Figure 5-6.) At the first off-page access, the wait states are controlled by the WS7 bit of the PWC1 register. At the second on-page access and onward, the wait states are controlled by the PWS bit of the PR register. The wait states can be also controlled by the READY pin. If the PS bit of the PRC register is 1 (page size is 8 bytes) in the 16-bit bus mode, the normal access (off-page) is executed at the first and fifth accesses, and on-page access is executed for the second through fourth, and sixth through eighth accesses. The number of wait states for each access is the same as that in the 32-bit bus mode. 60 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-6. Page-ROM Burst Cycle (32-bit bus mode) Note 1 Ta CLKOUT (output) Tb1 Tb1 Note 2 Ta2 Tb2 Note 2 Ta3 Tb3 Note 2 Ta4 Ts Ti BCYST (output) A2 - A23 (output) A1 A2 A3 A4 CS7 (output) MRD (output) D0 - D31 (input) 1 2 3 4 READY (input) Notes 1. off-page access 2. on-page access Remarks 1. 2. The dotted lines indicate the high-impedance state. The arrows indicate the sampling timing. 61 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-7. Page-ROM Burst Cycle (16-bit bus mode, 8-byte page size) Note 1 Ta Note 2 Note 2 Note 2 Note 1 Note 2 Note 2 Note 2 Ti Tb1 Tb1 Twa1 Twb1 Ta2 Tb2 Twa2 Twb2 Ta3 Tb3 Tb3 Twa3 Twb3 Ta4 Tb4 Twa4 Ts CLKOUT (output) BCYST (output) A2 - A23 (output) A1 A2 A3 A4 A5 A6 A7 A8 CS7 (output) MRD (output) D0 - D31 (input) 1 2 3 4 5 6 7 8 READY (input) Notes 1. off-page access 2. on-page access Remarks 1. 2. The dotted lines indicate the high-impedance state. The arrows indicate the sampling timing. 62 CHAPTER 5 BUS CONTROL FUNCTION 5.5 DRAM Cycle The EDO DRAM cycle is executed when the block 0 area of the memory space is accessed. The EDO DRAM cycle is classified into the following types by the length of data successively accessed, on-page/off-page, CAS cycle period, and data bus width. (1) Classification by length of data successively accessed * Single cycle (access unit: 4/2/1 byte) * DRAM access by execution of ST Instruction * DRAM access by execution of LD instruction to uncacheable area or instruction fetch * DRAM access by 2-cycle transfer of DMA * Burst cycle (access unit: 16 bytes) * DRAM access by refilling instruction/data cache * DRAM access by execution of instruction that transfers blocks with internal RAM (2) Classification by on-page/off-page * on-page cycle * RAS active and same row address as preceding DRAM cycle * off-page cycle * RAS inactive * RAS active and different row address from preceding DRAM cycle (3) Classification by CAS cycle period The CAS cycle period is set by the CRWT bit of the DRC register during read/write. * 1-clock CAS cycle * CRWT bit = 00 * CRWT bit = 10 (write cycle only) * 2-clock CAS cycle * CRWT bit = 11 * CRWT bit = 10 (read cycle only) 63 CHAPTER 5 BUS CONTROL FUNCTION (4) Classification by data bus width The data bus width is set by the BW0 bit of the DBC register. * When BW0 bit = 0: 32-bit bus mode * When BW0 bit = 1: 16-bit bus mode Figure 5-8. Example of Connection with 16M EDO-DRAM (1M x 16) (in 16-bit bus mode) V831 A0 - A10 D0 - D15 RAS LLCAS LUCAS WE OE 1M x 16 EDO-DRAM A0 - A9 I/O1 - I/O16 RAS LCAS UCAS WE OE Figure 5-9. Example of Connection with 16M EDO-DRAM (1M x 16) (in 32-bit bus mode) V831 A2 - A11 D0 - D15 RAS LLCAS LUCAS WE OE 1M x 16 EDO-DRAM A0 - A9 I/O1 - I/O16 RAS LCAS UCAS WE OE 1M x 16 EDO-DRAM A0 - A9 D16 - D31 I/O1 - I/O16 RAS ULCAS UUCAS LCAS UCAS WE OE 64 CHAPTER 5 BUS CONTROL FUNCTION 5.5.1 DRAM single cycle This cycle is started to access block 0 by executing the ST instruction or uncacheable LD instruction, or instruction fetch or DMA2 cycle transfer. Figure 5-10 shows the timing of the single 1-clock CAS off-page/on-page cycle, and Figure 5-11 shows the timing of the single 2-clock CAS off-page/on-page cycle. In the case of the 1-clock CAS cycle, the cycle for on-page access is a 2-bus clock cycle of Tc and Tce. Tc is a CAS assert state and Tce is a CAS cycle end state. Because the RAS signal is precharged during off-page access, at least three states, Trm (ROW miss state), Trp (RAS precharge state), and Trc (RAS-CAS state), are inserted before the on-page access. In the case of the 2-clock CAS cycle, the cycle for the on-page access is a 3-bus clock cycle of Tca, Tcn, and Tce. Tca is a CAS assert state, Tcn is a CAS negate state, and Tce is a CAS cycle end state. Trc (RAS-CAS state), are inserted before the on-page access. One state of Ti cycle is forcibly inserted after the read cycle started by the CPU. Because RAS is precharged during the off-page access, at least three states, Trm (ROW miss state), Trp (RAS precharge state), and 65 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-10. DRAM Single 1-Clock CAS on-page/off-page Cycle (32-bit bus mode) EDO off-page Trm CLKOUT (output) Trp Trc Tc Tce Ti EDO on-page Tc Tce BCYST (output) A2 - A23 (output) RA CA CA RAS (output) xxCAS (output) OE (output) Read D0 - D31 (input) WE (output) Write D0 - D31 (output) Remarks 1. 2. 3. xxCAS: LLCAS, LUCAS, ULCAS, UUCAS The dotted lines indicate the high-impedance state. The arrows indicate the sampling timing. 66 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-11. DRAM Single 2-Clock CAS on-page/off-page Cycle (32-bit bus mode) EDO off-page Trm CLKOUT (output) Trp Trc Tca Tcn Tce Ti EDO on-page Tca Tcn Tce BCYST (output) A2 - A23 (output) RA CA CA RAS (output) xxCAS (output) OE (output) Read D0 - D31 (input) WE (output) Write D0 - D31 (output) Remarks 1. 2. 3. xxCAS: LLCAS, LUCAS, ULCAS, UUCAS The dotted lines indicate the high-impedance state. The arrows indicate the sampling timing. 67 CHAPTER 5 BUS CONTROL FUNCTION 5.5.2 DRAM burst cycle The DRAM burst cycle is started when block 0 is accessed by refilling the instruction/data cache, or executing an instruction that transfers blocks with the internal RAM. This is a 16-byte successive bus cycle. Page access is executed from the second access and onward. Figure 5-12 shows the burst 1-clock CAS off-page cycle, and Figure 5-13 shows the burst 1-clock CAS on-page cycle. Figure 5-14 shows the timing of the burst 2-clock CAS off-page cycle, and Figure 5-15 shows the timing of the burst 2-clock CAS on-page cycle. In the case of the 1-clock CAS cycle, the cycle for on-page access is a 5-bus clock cycle (Tc through Tc4, and Tce) . Tc through Tc4 are the CAS assert states for four accesses, and Tce is a CAS cycle end state. Because the RAS signal is precharged during off-page access, at least three states (Trm, Trp, and Trc) are inserted before the onpage access. In the case of the 2-clock CAS cycle, the cycle for the on-page access is a 9-bus clock cycle (Tca through Tcn4 and Tce). Tca through Tca4 are CAS assert state for four accesses, Tcn1 through Tcn4 are CAS negate states, and Tce is a CAS cycle end state. Because RAS is precharged during the off-page access, at least three states (Trm, Trp, and Trc) are inserted before the on-page access. 68 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-12. DRAM Burst 1-Clock CAS off-page Cycle (32-bit bus mode) Trm CLKOUT (output) Trp Trc Tc Tc2 Tc3 Tc4 Tce BCYST (output) A2 - A23 (output) RA CA1 CA2 CA3 CA4 RAS (output) xxCAS (output) OE (output) Read D0 - D31 (input) 1 2 3 4 WE (output) Write D0 - D31 (output) 1 2 3 4 Remarks 1. 2. 3. xxCAS: LLCAS, LUCAS, ULCAS, UUCAS The dotted lines indicate the high-impedance state. The arrows indicate the sampling timing. 69 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-13. DRAM Burst 1-Clock CAS on-page Cycle (32-bit bus mode) Tc CLKOUT (output) Tc2 Tc3 Tc4 Tce BCYST (output) A2 - A23 (output) CA1 CA2 CA3 CA4 RAS (output) xxCAS (output) OE (output) Read D0 - D31 (input) 1 2 3 4 WE (output) Write D0 - D31 (output) 1 2 3 4 Remarks 1. 2. 3. xxCAS: LLCAS, LUCAS, ULCAS, UUCAS The dotted lines indicate the high-impedance state. The arrows indicate the sampling timing. 70 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-14. DRAM Burst 2-Clock CAS off-page Cycle (32-bit bus mode) Trm CLKOUT (output) Trp Trc Tca Tcn1 Tca2 Tcn2 Tca3 Tcn3 Tca4 Tcn4 Tce BCYST (output) A2 - A23 (output) RA CA1 CA2 CA3 CA4 RAS (output) xxCAS (output) OE (output) Read D0 - D31 (input) 1 2 3 4 WE (output) Write D0 - D31 (output) 1 2 3 4 Remarks 1. 2. 3. xxCAS: LLCAS, LUCAS, ULCAS, UUCAS The dotted lines indicate the high-impedance state. The arrows indicate the sampling timing. 71 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-15. DRAM Burst 2-Clock CAS on-page Cycle (32-bit bus mode) Tca CLKOUT (output) Tcn1 Tca2 Tcn2 Tca3 Tcn3 Tca4 Tcn4 Tce BCYST (output) A2 - A23 (output) CA1 CA2 CA3 CA4 RAS (output) xxCAS (output) OE (output) Read D0 - D31 (input) 1 2 3 4 WE (output) Write D0 - D31 (output) 1 2 3 4 Remarks 1. 2. 3. xxCAS: LLCAS, LUCAS, ULCAS, UUCAS The dotted lines indicate the high-impedance state. The arrows indicate the sampling timing. 5.5.3 Timing control For DRAM access timing control of the V831, a RAS precharge period and RAS-CAS delay period can be set in addition to the CAS cycle period. Note, however, that the wait states cannot be controlled by the READY pin during DRAM access. (1) Control during RAS precharge period The RAS precharge period is set by using the RP bit of the DRC register. When the RP bit is cleared to 0, the RAS precharge period is 2 bus clocks; when the RP bit is set to 1, the RAS precharge period is 3 bus clocks. Figure 5-16 shows the RAS precharge period when the RP bit is set to 1. 72 CHAPTER 5 BUS CONTROL FUNCTION (2) RAS-CAS delay time The RAS-CAS delay period during read is set by the RCD bit of the DRC register. When the RCD bit is cleared to 0, the RAS-CAS delay time is 1.5 bus clocks; when the RCD bit is set to 1, it is 2.5 bus clocks. The timing shown in Figure 5-16 is when the RCD bit is 1. Figure 5-16. DRAM Access Timing (burst off-page cycle) Trm Trp Trp Trc Trc Tca Tcn1 Tca2 Tcn2 Tca3 Tcn3 Tca4 Tcn4 Tce CLKOUT (output) BCYST (output) A2 - A23 (output) RA CA1 CA2 CA3 CA4 RAS (output) RP = 1 xxCAS (output) RCD = 1 OE (output) Read D0 - D31 (input) WE (output) Write D0 - D31 (output) 1 2 3 4 1 2 3 4 Remarks 1. 2. 3. xxCAS: LLCAS, LUCAS, ULCAS, UUCAS The dotted lines indicate the high-impedance state. The arrows indicate the sampling timing. 73 CHAPTER 5 BUS CONTROL FUNCTION 5.5.4 Byte access control The four xxCAS signals (UUCAS, ULCAS, LUCAS, and LLCAS) are used to control byte access. When the data bus is 32 bits wide, all the four xxCAS signals are used. When the data bus is 16 bits wide, however, only two xxCAS signals (LUCAS and LLCAS) are used. Tables 5-3 and 5-4 show the relations between the xxCAS signals and access addresses. xxCAS) Table 5-3. 32-Bit Data Bus (xx xx Address Data Size A1 Byte 0 0 1 1 Half word (16 bits) 0 1 Word (32 bits) 0 A0 0 1 0 1 0 0 0 UUCAS 1 1 1 0 1 0 0 ULCAS 1 1 0 1 1 0 0 LUCAS 1 0 1 1 0 1 0 LLCAS 0 1 1 1 0 1 0 xxCAS xxCAS) Table 5-4. 16-Bit Data Bus (xx xx Address Data Size A0 Byte 0 1 Half word (16 bits) Word (32 bits) First Second 0 0 0 UUCAS 1 1 1 1 1 ULCAS 1 1 1 1 1 LUCAS 1 0 0 0 0 LLCAS 0 1 0 0 0 xxCAS Remarks 1: High-level output 0: Low-level output 74 CHAPTER 5 BUS CONTROL FUNCTION 5.5.5 Refresh control The CBR refresh cycle and CBR self-refresh cycle can be automatically generated. (1) CBR refresh cycle Figure 5-17 shows the timing of the CBR refresh cycle. The RAS active period of the CBR refresh cycle can be set by the RFW bit of the RFC register. The RAS precharge period is set by the RP bit of the DRC register. The wait states cannot be controlled by the READY pin. Table 5-5. RAS Active Period RFC Register RFW1 0 0 1 RFW0 0 1 0 3 bus clocks 4 bus clocks 5 bus clocks RAS Active Period Figure 5-17. CBR Refresh Cycle (when RFW1, 0 = 01, RP = 1) CBR refresh CLKOUT (output) RAS (output) RAS precharge period: 3 clocks RAS width period: 4 clocks xxCAS (output) REFRQ (output) Remark xxCAS: LLCAS, LUCAS, ULCAS, UUCAS 75 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-18. CBR Refresh Cycle (when RFW1, 0 = 00, RP = 0) CBR refresh CLKOUT (output) RAS width period: 3 clocks RAS (output) RAS precharge period: 2 clocks xxCAS (output) REFRQ (output) Remark xxCAS: LLCAS, LUCAS, ULCAS, UUCAS (2) CBR self-refresh cycle The CBR self-refresh cycle is generated in the STOP mode. The self-refresh cycle is started when the STBY instruction is executed with the REN bit of the RFC register set to 1. The self-refresh cycle is cleared by using the RESET or NMI pin. Figure 5-19 shows the timing of the CBR self-refresh cycle. The RAS precharge period (tRPS) after the CBR self refresh is at least 5 bus clocks. Figure 5-19. CBR Self-Refresh Cycle (when cleared by NMI, RP = 0) CBR self refresh CLKOUT (output) RAS (output) RAS precharge period: 2 clocks 5 clocks to secure tRPS xxCAS (output) REFRQ (output) Remark xxCAS: LLCAS, LUCAS, ULCAS, UUCAS 76 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-20. CBR Self-Refresh Cycle (when cleared by RESET, RP = 0) CBR self refresh CLKOUT (output) RAS (output) RAS precharge period: 2 clocks xxCAS (output) REFRQ (output) Remark xxCAS: LLCAS, LUCAS, ULCAS, UUCAS 5.6 Idle State The number of idle states for block n after the read cycle is set by using the ISn bit (n = 0 to 7) of the PIC register. The values of the bus control signals during the idle period are shown below. Table 5-6. Values of Bus Control Signals during Idle Period Signal Name A1 - A23 D0 - D31 RAS UUMWR, ULMWR, LUMWR, LLMWR, MRD, CS1 - CS7, IORD, IOWR, BCYST, UUCAS, ULCAS, LUCAS, LLCAS, WE, OE Signal Value Retains value in preceding cycle High impedance Retains value in preceding cycle Inactive 5.7 Bus Sizing The V831 has a bus sizing function that changes the bus width between 32 bits and 16 bits. When 32-bit data is accessed via the 16-bit data bus in the single cycle, access is made two times. If 32-bit data is accessed via the 16bit data bus in the burst cycle, access takes place eight times in a row. The timing when the DRAM is accessed in word units in the single cycle with a data bus width of 16 bits (refer to Figure 5-21), the timing when the DRAM is accessed in the burst cycle (refer to Figure 5-22), the timing when the I/O is accessed in word units (refer to Figure 5-23), and the timing when the SRAM is accessed in word units in the single cycle (refer to Figure 5-24) are shown below. 77 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-21. Additional Access in DRAM Single Cycle due to Bus Sizing Trm CLKOUT (output) Trp Trc Tc Twc Tce BCYST (output) A1 - A23 (output) RA CA1 CA2 RAS (output) LUCAS, LLCAS (output) OE (output) Read D0 - D15 (input) 1 2 WE (output) Write D0 - D15 (output) 1 2 Remarks 1. 2. The dotted lines indicate the high-impedance state. The arrows indicate the sampling timing. 78 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-22. Additional Access in DRAM Burst Cycle due to Bus Sizing Tc CLKOUT (output) Twc Tc2 Twc2 Tc3 Twc3 Tc4 Twc4 Tce BCYST (output) A1 - A23 (output) CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 RAS (output) LUCAS, LLCAS (output) OE (output) Read D0 - D15 (input) 1 2 3 4 5 6 7 8 WE (output) Write D0 - D15 (output) 1 2 3 4 5 6 7 8 Remarks 1. 2. The dotted lines indicate the high-impedance state. The arrows indicate the sampling timing. 79 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-23. Additional Access in I/O Cycle due to Bus Sizing Ta CLKOUT (output) Tss Tss Twa Ts Ts BCYST (output) A1 - A23 (output) CSn (output) IORD (output) Read D0 - D15 (input) IOWR (output) Write D0 - D15 (output) READY (input) Remarks 1. 2. 3. n = 1 to 7 The dotted lines indicate the high-impedance state. The arrows indicate the sampling timing. 80 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-24. Additional Access in SRAM Single Cycle due to Bus Sizing Ta CLKOUT (output) Tss Tss Twa Ts Ts BCYST (output) A1 - A23 (output) CSn (output) MRD (output) Read D0 - D15 (input) xxMWR (output) Write D0 - D15 (output) READY (input) Remarks 1. 2. 3. 4. n = 1 to 7 xxMWR: LLMWR, LUMWR, ULMWR, UUMWR The dotted lines indicate the high-impedance state. The arrows indicate the sampling timing. 81 CHAPTER 5 BUS CONTROL FUNCTION 5.8 Bus Hold Cycle An external bus master can request the V831 for the bus mastership by asserting the HLDRQ signal active. The V831 arbitrates the bus, asserts the HLDAK signal active, and releases the bus. When the HLDRQ signal is asserted active, a bus hold request is accepted after one bus clock cycle, and the idle cycle (Ti) is started. After the idle cycle (Ti) has been executed for one bus clock cycle, the bus hold cycle (Th) is started, and the bus goes into a highimpedance state (refer to Figure 5-25). After the bus hold cycle, the RAS signal is deasserted inactive. Bus hold is not released by the NMI signal. Figure 5-25. Bus Hold Cycle Bus hold cycle Ti CLKOUT (output) Th Th Th Th Ti HLDRQ (input) HLDAK (output) BCYST (output) WE , OE (output) A2 - A23, CS1 - CS7 (output) RAS (output) xxCAS (output) MRD, xxMWR (output) D0 - D31 (I/O) Remarks 1. xxCAS : LLCAS, LUCAS, ULCAS, UUCAS 2. xxMWR: LLMWR, LUMWR, ULMWR, UUMWR 3. The dotted lines indicate the high-impedance state. 4. The arrows indicate the sampling timing. 82 CHAPTER 5 BUS CONTROL FUNCTION 5.9 Bus Arbitration The V831 performs bus arbitration between two internal bus masters (CPU and DMA), DRAM refresh, and an external bus master. The priority of this bus arbitration is as follows: Bus lock > DRAM refresh = external bus master > DMA > CPU (1) Bus lock > external bus master The external bus master cannot acquire the bus mastership between the bus lock read cycle started by the CAXI instruction and bus lock write cycle. DRAM refresh is executed even during bus lock. (2) External bus master > DMA The external bus master can acquire the bus mastership during DMA transfer. DMA cannot acquire the bus mastership while the external bus master is using the bus. However, the external bus master cannot acquire the bus mastership between the read cycle of one DMA transfer and write cycle. (3) DRAM refresh > DMA If a DRAM refresh request is generated while DMA is executing demand transfer, the refresh request of DRAMC takes precedence, and refresh is executed. (4) DRAM refresh, external bus master If a DRAM refresh request is generated while the external bus master is using the bus, the refresh request is kept pending. The pending refresh request can be stored in the refresh request queue of the BCU up to seven times. When the external bus master has released the bus, refresh is executed by the number of times the refresh request has been stored in the refresh request queue. 83 CHAPTER 5 BUS CONTROL FUNCTION 5.10 Write Buffer Operation The V831 has four stages of internal write buffers to speed up the write operation. Therefore, the CPU can execute the next instruction without having to wait for the completion of the bus cycle that has been started by a store instruction. If all the write buffers are used, the store instruction waits until one of the write buffers becomes empty. A store instruction executed to write to the internal RAM does not wait because it does not use a write buffer. To ensure the sequential relation at memory access, all the contents of the write buffers are output to the external memory before processing is executed in the following cases: If a data cache miss occurs when a load instruction is executed. If the non-cache area is accessed by a load instruction. Similarly, all the contents of the write buffers are output to the external memory and then the instruction is executed in the following cases: I/O access instruction Block transfer instruction (BILD, BDLD, BIST, BDST) HALT, STBY, CAXI instructions The bus hold operation is performed regardless of the operations of the write buffers. If data written to the external memory is transferred by means of DMA, therefore, perform I/O write, etc., after execution of the last store instruction, output all the contents of the write buffers, and then execute the DMA transfer. 5.11 Memory Mapped I/O With the V831, there may be a time lag between the execution of the store instruction and the corresponding bus write operation. Therefore, care must be exercised if memory mapped I/O is used in critical timing. Note that the INT instruction extends zero while the LD instruction extends the sign. 84 CHAPTER 6 WAIT CONTROL FUNCTION The bus control unit (BCU) controls eight blocks respectively corresponding to seven CS signals to select a type of bus cycle, generate the CS signals, select data bus width, control wait states, and insert idle states. 6.1 * * * Features Controls 8 blocks in accordance with I/O and memory spaces Linear address space of each block: 16M bytes Bus cycle select function Block 0 Block 1, 2 Block 7 : EDO DRAM : SRAM (ROM) : Page-ROM or SRAM (ROM) selectable Blocks 3 through 6: I/O or SRAM (ROM) selectable * * Data bus width select function Data bus width selectable between 32 bits and 16 bits for each block Wait control function Block 0 Blocks 5 and 6 * Idle state insertion function 0 to 3 states for each block (bus clock) : EDO DRAM access timing controlable : 0 to 15 wait states Blocks 1 through 4 and 7 : 0 to 7 wait states 85 CHAPTER 6 WAIT CONTROL FUNCTION 6.2 Address Space and Block The internal 4G-byte memory and I/O spaces are divided into blocks with each block consisting of 16M bytes. The linear address space of each block is 16M bytes. Because addresses 60000000H through 7FFFFFFFH of the uncacheable area are used as the debug monitor space of the DCU, do not connect an external memory to this area. The image of each block overlaps the DCU-reserved area but there is no problem in terms of operation. However, do not map external devices to the addresses (60000000 through 7FFFFFFF) of the DCU-reserved area. Figure 6-1. Address Space Memory space FFFFFFFFH FE001000H FE000FFFH FE000000H I/O space External address space Image of block 7 Image of block 6 Image of block 5 Image of block 4 Image of block 3 Image of block 2 Image of block 1 Image of block 0 Internal instruction RAM Internal I/O area C0000000H BFFFFFFFH External I/O area 80000000H 7FFFFFFFH DCU-reserved area (A26-A24) 60000000H 5FFFFFFFH Uncacheable area 40000000H 3FFFFFFFH External I/O area Image of block 7 Image of block 6 Image of block 5 Image of block 4 Image of block 3 Image of block 2 Image of block 1 Image of block 0 Block 7 (16M) Block 6 (16M) Block 5 (16M) Block 4 (16M) Block 3 (16M) Block 2 (16M) Block 1 (16M) Block 0 (16M) Image of DRAM area 111 110 101 100 011 CS7 CS6 CS5 CS4 CS3 CS2 CS1 Memory Memory or I/O selection 128M bytes External I/O area 010 001 Memory 00001000H 00000000H Internal data RAM 000 DRAM area 86 CHAPTER 6 WAIT CONTROL FUNCTION 6.3 Wait Control Registers BCU has a bus cycle type control register (BCTC), data bus width control register (DBC), programmable wait control registers (PWC0 and PWC1) that perform wait control. 6.3.1 Bus cycle type control register (BCTC) This register sets the type of the bus cycle for blocks 3 through 7. However, the bus cycle of block 0 is fixed to the DRAM cycle, and the bus cycles of blocks 1 and 2 are fixed to SRAM/ROM cycles. This register can be read/written in 8-bit units. Figure 6-2. Bus Cycle Type Control Register (BCTC) Address: C0000010H 7 BCTC CT7 6 CT6 5 CT5 4 CT4 3 CT3 2 0 1 0 0 0 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R Bit 7 Bit Name CT7 Cycle Type7 Description When memory block 7 is accessed, the CS7 signal is output. This bit specifies the cycle to be started at that time. 0: SRAM (ROM) cycle 1: Page-ROM cycle 6-3 CT6 - CT3 Cycle Type6 - 3 These bits specify whether the CS6 through CS3 signals are output to the memory or I/O, or specify the cycle to be started. 0: SRAM (ROM) cycle 1: I/O cycle 87 CHAPTER 6 WAIT CONTROL FUNCTION 6.3.2 Data bus width control register (DBC) This register specifies the data bus width for blocks 0 through 6. It can be read/written in 8-bit units. However, the bus width of block 7 (CS7), where the normal boot ROM is placed, is specified by the value of the BT16B pin. Figure 6-3. Data Bus Width Control Register (DBC) Address: C0000012H 7 DBC 6 5 4 3 2 1 0 BW7 BW6 BW5 BW4 BW3 BW2 BW1 BW0 Initial value: R/W: BT16B 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W R Bit 7 Bit Name BW7 Bus Width Description This bit reads the value of the BT16B pin. The data bus width of block 7 (CS7) specified by the value of the BT16B pin is as follows: 0: 32-bit bus width 1: 16-bit bus width 6-0 BW6 - BW0 Bus Width These bits specify the data bus width of blocks 6 through 0: 0: 32-bit bus width 1: 16-bit bus width 88 CHAPTER 6 WAIT CONTROL FUNCTION 6.3.3 Programmable wait control register 0 (PWC0) This register sets the number of wait states used when blocks 1 through 3 are accessed. It can be read/written in 16-bit units. Up to seven wait states can be inserted. Block 0 is fixed to the DRAM area. The number of wait states when accessing the DRAM is specified by the DRAM configuration register (DRC). Figure 6-4. Programmable Wait Control Register 0 (PWC0) Address: C0000014H 15 PWC0 0 14 13 WS3 12 11 0 10 9 WS2 8 7 0 6 5 WS1 4 3 0 2 0 1 0 0 0 Initial value: R/W: 0 R 1 R/W 1 R/W 1 R/W 0 R 1 R/W 1 R/W 1 R/W 0 R 1 R/W 1 R/W 1 R/W 0 R 0 R 0 R 0 R Bit 14 - 12 Bit Name WS3 Wait States3 Description This bit specifies the number of wait states when block 3 (CS3) is accessed. The number of wait states is 0 to 7. WS3 0 0 0 0 10 - 8 WS2 0 0 1 1 0 1 0 1 Number of wait states 0 1 2 3 1 1 1 1 WS3 0 0 1 1 0 1 0 1 Number of wait states 4 5 6 7 Wait States2 This bit specifies the number of wait states when block 2 (CS2) is accessed. The number of wait states is 0 to 7. The method of setting the number of wait states is the same as that of WS3. 6-4 WS1 Wait States1 This bit specifies the number of wait states when block 1 (CS1) is accessed. The number of wait states is 0 to 7. The method of setting the number of wait states is the same as that of WS3. 89 CHAPTER 6 WAIT CONTROL FUNCTION 6.3.4 Programmable wait control register 1 (PWC1) This register specifies the number of wait states when blocks 4 through 7 are accessed. It can be read/written in 16-bit units. Up to seven wait states can be inserted when accessing blocks 4 and 7. Up to 15 wait states can be inserted when accessing blocks 5 and 6. Figure 6-5. Programmable Wait Control Register 1 (PWC1) Address: C0000016H 15 PWC1 0 14 13 WS7 12 11 10 WS6 9 8 7 6 WS5 5 4 3 0 2 1 WS4 0 Initial value: R/W: 0 R 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 R 1 R/W 1 R/W 1 R/W Bit 14 - 12 Bit Name WS7 Wait States7 Description This bit specifies the number of wait states when block 7 (CS7) is accessed. The number of wait states is 0 to 7. WS7 0 0 0 0 0 0 1 1 0 1 0 1 Number of wait states 0 1 2 3 1 1 1 1 WS7 0 0 1 1 0 1 0 1 Number of wait states 4 5 6 7 If the Page-ROM cycle is selected by the CT7 bit of the BCTC, the number of wait states is that in the single cycle or that in the burst cycle during off-page access. The number of wait states during on-page access can be specified by the PWS bit of PRC register. 11 - 8 WS6 Wait States6 This bit specifies the number of wait states when block 6 (CS6) is accessed. The number of wait states is 0 to 15. WS6 0 0 0 0 0 0 0 0 7-4 WS5 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Number of wait states 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 WS6 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Number of wait states 8 9 10 11 12 13 14 15 Wait States5 This bit specifies the number of wait states when block 5 (CS5) is accessed. The number of wait states is 0 to 15. The method of setting the number of wait states is the same as that of WS6 2-0 WS4 Wait States4 This bit specifies the number of wait states when block 4 (CS4) is accessed. The number of wait states is 0 to 7. The method of setting the number of wait states is the same as that of WS7. 90 CHAPTER 6 WAIT CONTROL FUNCTION 6.3.5 Programmable idle control register (PIC) This register specifies the number of idle states inserted after blocks 0 through 7 have been accessed for read. It can be read/written in 16-bit units. Up to three idle states can be inserted. When blocks 0 through 7 are accessed by the V830 CPU core, one idle state is always inserted after the read cycle. This idle state is counted as the set value of ISn of the PIC register. When ISn (n = 0 to 7) is 0 or 1, one idle state is inserted. However, the setting of the PIC register is valid even during 2-cycle transfer of DMA. Figure 6-6. Programmable Idle Control Register (PIC) Address: C0000018H 15 PIC IS7 14 13 IS6 12 11 IS5 10 9 IS4 8 7 IS3 6 5 IS2 4 3 IS1 2 1 IS0 0 Initial value: R/W: 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W Bit 15 - 0 Bit Name IS7 - IS0 Idle State7 - 0 Description These bits specify the number of idle states. IS7 through IS0 correspond to blocks 7 through 0, respectively. When the block corresponding to the CSn signal is accessed for read, the number of idle states specified by ISn (n = 0 to 7) is automatically inserted after read access. ISn 0 0 1 1 0 1 0 1 Number of inserted idle states 0 1 2 3 91 CHAPTER 6 WAIT CONTROL FUNCTION 6.4 Wait Control by READY Pin The V831 can control wait states to be inserted in cycles accessing the I/O, SRAM, and ROM area, by using the PWC0 and PWC1 registers, and READY pin. 6.4.1 Sampling timing of READY pin * I/O area: The READY pin is sampled at the rising edge of the Ts state. If the programmed number of wait states has not been completed, or if the READY pin is not active (if a wait state is inserted), the Ts cycle is repeated. * Single cycle of SRAM or ROM: repeated. * Burst cycle of SRAM or ROM: The READY pin is sampled at the rising edge of each Tb state and the rising edge of the Ts state. When a wait state is inserted, the Tb cycle or Ts cycle is repeated. * Page-ROM cycle: The READY pin is sampled at the rising edge of the Tb state and the rising edge of the Ts state. When a wait state is inserted, the Tb cycle or Ts cycle is repeated. A different number of wait states can be programmed in the on-page mode and off-page mode. 6.4.2 When using both READY pin and programmable wait The number of wait states set by the PWC0 and PWC1 registers and the number of wait states set by using the READY pin is logically ORed. Therefore, the larger number of wait states is inserted. When performing wait control by using the READY pin, the wait cycle is not cleared even if the READY pin is deasserted inactive at the above sampling timing, until the programmed number of wait states has been inserted. The wait cycle is not cleared unless the READY pin is inactive in the Ts state after the programmed wait cycle, even if the READY pin is deasserted inactive before the programmed wait cycle is cleared. When performing wait control by using the READY pin, therefore, it is recommended to set the number of waits states of the PWC0 and PWC1 registers for the corresponding block to 0 to avoid confusion. * DRAM cycle: The wait state cannot be controlled by the RESET pin input. The precharge period, RAS - CAS delay time, and CAS cycle period are programmable. For details, refer to 5.5 DRAM Cycle and CHAPTER 7 MEMORY ACCESS CONTROL FUNCTION. The READY pin is sampled at the rising edge of the Ts state. If the programmed number of times of wait has not been completed, or if the READY pin is not active, the Ts cycle is 92 CHAPTER 7 MEMORY ACCESS CONTROL FUNCTION This chapter explains the DRAM control function and Page-ROM control function. The BCU of the V831 can be directly connected to EDO DRAM, Page-ROM, and SRAM (ROM). The EDO DRAM is accessed by using the address bus, data bus, and four xxCAS signals, RAS, OE, and WE signals. An address of the DRAM is output from the address pins with the row address and column address multiplexed. Page access to the Page-ROM is enabled in the burst access mode. The page size can be selected from 8 or 16 bytes. The SRAM (ROM) is accessed by using the address bus and data bus, four xxMWR signals, MRD, and CS signals. Remarks 1. xxCAS: UUCAS, ULCAS, LUCAS, LLCAS 2. xxMWR: UUMWR, ULMWR, LUMWR, LLMWR 7.1 Features * * * * DRAM control function Generation of RAS, LLCAS, LUCAS, ULCAS, UUCAS, REFRQ, OE, WE signals 8, 9, and 10 multiplexed address bits DRAM access timing control CAS access period : 1 or 2 bus clocks selectable RAS-CAS delay period : 1.5 or 2.5 bus clocks selectable RAS precharge period : 2 or 3 bus clocks selectable * CBR refresh and CBR self-refresh functions Page size Wait control during page access : 8 or 16 bytes : 0 or 1 wait state * Page-ROM control function * * 7.2 DRAM Control Function The BCU generates RAS, LLCAS, LUCAS, ULCAS, UUCAS, REFRQ, OE, and WE signals and controls access to the DRAM. Addresses are output to the DRAM from the address pins by multiplexing row and column addresses. The connected DRAM must be of x8 bits or more and have a hyper page mode (EDO). The refresh mode is a CAS-before-RAS (CBR) mode, and the refresh cycle can be arbitrarily set. CBR self refresh is performed in the STOP mode. 93 CHAPTER 7 MEMORY ACCESS CONTROL FUNCTION 7.2.1 Address multiplex function Row addresses and column addresses are multiplexed, as shown in Figure 7-1, in the DRAM cycle, depending on the values of the DAW bit of the DRAM configuration register (DRC). a1 through a23 in this figure indicate the addresses output by the CPU, and A1 through A23 indicate the address pins of the V831. Figure 7-1. Output of Row Address and Column Address Address pins A23 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 DAW = 10 a23 a15 a14 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 DAW = 01 a23 a15 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 DAW = 00 a23 a15 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 Column address a23 a1 7.2.2 Judgment of on-page/off-page If the RAS signal is active when page access is enabled because the HPAE bit of the DRAM configuration register (DRC) is 1, whether the DRAM access to be started is in the same page as the previous DRAM access. Table 7-1 shows the relation between an address to be compared and address shift. Table 7-1. Address Compared by on-page/off-page Judgment Data Bus Width Address Shift 16 bits 8 9 10 a23 - a9 a23 - a10 a23 - a11 32 bits a23 - a10 a23 - a11 a23 - a12 7.2.3 DRAM configuration register (DRC) This register sets an address multiplex width during DRAM access, and the output timing of the RAS and CAS signals. It can be read/written in 8-bit units. 94 CHAPTER 7 MEMORY ACCESS CONTROL FUNCTION Figure 7-2. DRAM Configuration Register (DRC) Address: C0000020H 7 DRC 6 5 RCD 4 3 2 0 1 DAW 0 HPAE RP CRWT Initial value: R/W: 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 R 0 R/W 1 R/W Bit 7 Bit Name HPAE Hyper Page Mode Enable Description This bit controls start of page access supporting the hyper page mode of the DRAM. However, page access cannot be disabled when the DRAM is accessed the second time and onward in the burst cycle. 0: Disables start (off-page access is always performed). 1: Enables start (start of on-page access is enabled). 6 RP RAS Precharge Sets the precharge period of RAS. 0: 2 bus clocks 1: 3 bus clocks 5 RCD RAS-CAS Delay Sets RAS-CAS delay time. 0: 1.5 bus clocks 1: 2.5 bus clocks 4, 3 CRWT CAS Read Write Timing Sets the CAS cycle period during DRAM read/write. CRWT 0 0 1 1 1, 0 DAW 0 1 0 1 CAS cycle time Read cycle 1 bus clock Setting prohibited 2 bus clocks 2 bus clocks 1 bus clock Write cycle DRAM Address Width Sets an address width for a column address in the DRAM cycle. DAW 0 0 1 1 0 1 0 1 8 bits 9 bits 10 bits Setting prohibited Address width 95 CHAPTER 7 MEMORY ACCESS CONTROL FUNCTION 7.2.4 Refresh function The BCU can automatically generate the distributed CBR refresh cycle necessary for refreshing the external DRAM. Whether refreshing is enabled or disabled and the refresh interval are set by the refresh control register (RFC). The BCU has a refresh request queue that can store refresh requests up to seven times. (1) Refresh request queue The BCU has a refresh request queue that can store refresh requests up to seven times. When the bus is released, the refresh cycle is successively generated until the contents of the refresh request queue reach "0". If a refresh request is generated when the contents of the refresh request queue are "7", the contents of the queue are not changed and remain "7". (2) Refresh control register (RFC) The refresh control register (RFC) enables or disables refreshing, and sets the length of the refresh cycle and refresh interval. The RFC register can be read/written in 16-bit units. The refresh interval can be calculated by the following expression: Refresh interval (s) = Refresh count clock (tRCY) x Interval factor (RI) The refresh count clock and interval factor are specified by the RCC bit and RI bit of the RFC register. Because the BCU always asserts the RAS signal active after the DRAM has been accessed, if the refresh cycle is longer than the maximum value of the RAS pulse width (tRAS), keep the refresh cycle shorter than the maximum value of tRAS. Caution To change the setting of the RI bit of the RFC register, be sure to disable refreshing by using the REN bit, and then change the content of the RI bit. 96 CHAPTER 7 MEMORY ACCESS CONTROL FUNCTION Figure 7-3. Refresh Control Register (RFC) Address: C0000022H 15 RFC REN 14 0 13 0 12 RFTC 11 10 9 RCC 8 7 0 6 5 4 3 RI 2 1 0 RFW Initial value: R/W: 1 R/W 0 R 0 R 1 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 15 Bit Name REN Refresh Enable Description Enables or disables CBR refresh and CBR self refresh. 0: Disables CBR refresh and CBR self refresh 1: Enables CBR refresh and CBR self refresh 12 RFTC Refresh Request Terminal Count Selects output of REFRQ/TC. 0: TC output 1: REFRQ output 11, 10 RFW Refresh Wait Sets the RAS active period of the CBR refresh cycle. RFW 0 0 1 1 9, 8 RCC 0 1 0 1 3 bus clocks 4 bus clocks 5 bus clocks Setting prohibited RAS active period Refresh Count Clock Specifies a refresh count clock (tRCY). indicates the frequency of the internal bus clock. RCC 0 0 1 6-0 RI 0 1 32/ 128/ Setting prohibited Refresh count clock (tRCY) Refresh Interval Sets the interval factor of the interval timer for refresh timing generation. RI 0 0 : 1 0 0 : 1 0 0 : 1 0 0 : 1 0 0 : 1 0 1 : 1 Interval factor 1 2 : 128 97 CHAPTER 7 MEMORY ACCESS CONTROL FUNCTION 7.3 Page-ROM Control Function The BCU controls page access to the Page-ROM. The page size and the number of wait states during page access can be set by using the Page-ROM configuration register (PRC). 7.3.1 Page-ROM configuration register (PRC) This register sets the number of wait states during on-page access of the Page-ROM and the page size. This register is valid only when the Page-ROM cycle is started for block 7. Figure 7-4. Page-ROM Configuration Register (PRC) Address: C0000024H 7 PRC 0 6 0 5 0 4 0 3 0 2 0 1 PWS 0 PS Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 1 R/W 1 R/W Bit 1 Bit Name PWS Page-ROM Wait States Description Sets the number of wait states during on-page access of the Page-ROM. 0 : 0 wait 1 : 1 wait This bit is valid only when the Page-ROM cycle is selected by the CT7 bit of the BCTC register. The number of wait states during off-page access is in accordance with the setting of the WS7 bit of the PWC1 register. 0 PS Page Size Sets the page size of the Page-ROM. PS 0 16 bytes This setting is valid in the 16-/32-bit bus mode. In both the modes, the first access in the burst cycle is off-page access. 1 8 bytes This setting is valid only in the 16-bit bus mode. In the burst cycle in which access is made eight times in a row, the first and fifth accesses are off-page accesses. This setting is ignored in the 32-bit bus mode. In the burst cycle in which access is made four times in a row, only the first access is off-page access. Page size 98 CHAPTER 8 DMA FUNCTION The V831 has a DMA (Direct Memory Access) controller that executes and control DMA transfer. The DMAC (DMA controller) transfers data between memory and I/O or between memory areas according to a DMA request issued by the internal peripheral hardware (serial interface and timer) or external DMARQ pin, or by means of software trigger. 8.1 * * * * * Features Four independent DMA channels Transfer unit: Bytes, half words (2 bytes), words (4 bytes) Maximum number of transfers: 16,777,216 (2 ) times Transfer type: 2-cycle transfer Two transfer modes * * 24 Single transfer mode Demand transfer mode External DMARQ pin (x 4) Request from internal peripheral hardware (serial interface (x 3 channels) and timer) Request from software Between memory and I/O Between memory and memory * Transfer request * * * * Transfer source and destination * * * * Programmable wait function DMA transfer end output signal (TC) 99 CHAPTER 8 DMA FUNCTION 8.2 Configuration Figure 8-1. DMAC Block Diagram DMAC Internal I/O Bus interface ROM Internal peripheral I/O bus BCU DMA source address register (DSA) External bus RAM Address control block DMA destination address register (DDA) I/O Counter control block DMA transfer count register (DBC) I/O Channel control block DMA control register (DCHC, DC) DMARQ0 - 3 100 DMAAK0 - 3 INTDMA INTCM4 INTCSI INTSR INTST TC CHAPTER 8 DMA FUNCTION 8.3 DMA Control Registers 8.3.1 DMA source address registers 0 through 3 (DSA0 through DSA3) These registers specify the DMA transfer source addresses (32 bits) of DMA channels 0 through 3. Each of these registers consist of two 16-bit registers: DSAnH and DSAnL (n = 0 to 3). Set an address value in accordance with the DMA transfer data size (set by the DCHC register) (half-word transfer: multiple of 2, word transfer: multiple of 4). The next DMA transfer source address is held during DMA transfer. (1) DMA source address registers 0H through 3H (DSA0H through DSA3H) Figure 8-2. DMA Source Address Registers 0H through 3H (DSA0H through DSA3H) Address of DSA0H: C0000030H Address of DSA1H: C0000040H Address of DSA2H: C0000050H Address of DSA3H: C0000060H 15 DSA0H - 3H 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SA31 SA30 SA29 SA28 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 Initial value: R/W: - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W Bit 15 - 8 Bit Name SA31 - SA24 Source Address Description These bits specify the address (A31 through A24) of the DMA transfer source. They hold the next DMA transfer source address during DMA transfer. Caution Although a 32-bit address is specified, only 24 bits of the address, A23 through A1, are output to an external device. Therefore, the width of the counter is 24 bits and bits SA31 through SA24 are fixed. This means that data cannot be transferred over blocks corresponding to the chip select signals. 7-0 SA23 - SA16 Source Address These bits specify the address (A23 through A16) of the DMA transfer source. They hold the next DMA transfer source address during DMA transfer. 101 CHAPTER 8 DMA FUNCTION (2) DMA source address registers 0L through 3L (DSA0L through DSA3L) Figure 8-3. DMA Source Address Registers 0L through 3L (DSA0L through DSA3L) Address of DSA0L: C0000032H Address of DSA1L: C0000042H Address of DSA2L: C0000052H Address of DSA3L: C0000062H 15 DSA0L - 3L 14 13 12 11 10 9 8 SA8 7 SA7 6 SA6 5 SA5 4 SA4 3 SA3 2 SA2 1 SA1 0 SA0 SA15 SA14 SA13 SA12 SA11 SA10 SA9 Initial value: R/W: - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W Bit 15 - 0 Bit Name SA15 - SA0 Source Address Description These bits specify the address (A15 through A0) at the DMA transfer source. They hold the next DMA transfer source address during DMA transfer. 102 CHAPTER 8 DMA FUNCTION 8.3.2 DMA destination address registers 0 through 3 (DDA0 through DDA3) These registers specify the DMA transfer destination addresses (32 bits) of DMA channels 0 through 3. Each of these registers consist of two 16-bit registers: DDAnH and DDAnL (n = 0 to 3). Set an address value in accordance with the DMA transfer data size (set by the DCHC register) (half-word transfer: multiple of 2, word transfer: multiple of 4). They hold the next DMA transfer destination address during DMA transfer. (1) DMA destination address registers 0H through 3H (DDA0H through DDA3H) Figure 8-4. DMA Destination Address Registers 0H through 3H (DDA0H through DDA3H) Address of DDA0H: C0000034H Address of DDA1H: C0000044H Address of DDA2H: C0000054H Address of DDA3H: C0000064H 15 DDA0H - 3H 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DA31 DA30 DA29 DA28 DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 Initial value: R/W: - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W Bit 15 - 8 Bit Name DA31 - DA24 Destination Address Description These bits specify the address (A31 through A24) of the DMA transfer destination. They hold the next DMA transfer destination address during DMA transfer. Caution Although a 32-bit address is specified, only 24 bits of the address, A23 through A1, are output to an external device. Therefore, the width of the counter is 24 bits and bits DA31 through DA24 (8 bits) are fixed. This means that data cannot be transferred over blocks corresponding to the chip select signals. 7-0 DA23 - DA16 Destination Address These bits specify the address (A23 through A16) of the DMA transfer destination. They hold the next DMA transfer destination address during DMA transfer. 103 CHAPTER 8 DMA FUNCTION (2) DMA destination address registers 0L through 3L (DDA0L through DDA3L) Figure 8-5. DMA Destination Address Registers 0L through 3L (DDA0L through DDA3L) Address of DDA0L: C0000036H Address of DDA1L: C0000046H Address of DDA2L: C0000056H Address of DDA3L: C0000066H 15 DDA0L - 3L 14 13 12 11 10 9 8 DA8 7 DA7 6 DA6 5 DA5 4 DA4 3 DA3 2 DA2 1 DA1 0 DA0 DA15 DA14 DA13 DA12 DA11 DA10 DA9 Initial value: R/W: - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W Bit 15 - 0 Bit Name DA15 - DA0 Destination Address Description These bits specify the address (A15 through A0) at the DMA transfer destination. They hold the next DMA transfer destination address during DMA transfer. 8.3.3 DMA byte count registers 0 through 3 (DBC0 through DBC3) These registers specify the number of times of byte transfer (24 bits) by DMA channels 0 through 3. Each of these registers consists of two 16-bit registers: DBCnH and DBCnL (n = 0 to 3). These registers hold the remaining number of times byte transfer is to be executed during DMA transfer. The values by which the values of these registers are decremented during byte, half word, and word transfer are shown below. Transfer ends when a borrow occurs. Byte transfer Word transfer : : Decremented by one [Setting] Number of transfers - 1 Decremented by two [Setting] (Number of transfers - 1) x 2 Decremented by four [Setting] (Number of transfers - 1) x 4 Half word transfer: 104 CHAPTER 8 DMA FUNCTION Figure 8-6. DMA Byte Count Registers 0 through 3 (DBC0 through DBC3) (1) DMA byte count registers 0H through 3H (DBC0H through DBC3H) Address of DBC0H: C0000038H Address of DBC1H: C0000048H Address of DBC2H: C0000058H Address of DBC3H: C0000068H 15 DBC0H - 3H 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 6 5 4 BC 3 2 1 0 Initial value: R/W: - R - R - R - R - R - R - R - R - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W (2) DMA byte count registers 0L through 3L (DBC0L through DBC3L) Address of DBC0L: C000003AH Address of DBC1L: C000004AH Address of DBC2L: C000005AH Address of DBC3L: C000006AH 15 DBC0L - 3L 14 13 12 11 10 9 8 BC 7 6 5 4 3 2 1 0 Initial value: R/W: - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W Bit 7 - 0: DBCnH Bit Name BC Byte Count Description 15 - 0: DBCnL These bits specify the number of times of byte transfer. They hold the remaining number of times byte transfer is to be executed during DMA transfer. Bit 7 of the DBCnH register is the MSB, and bit 0 of the DBCnL register is the LSB (n = 0 to 3). BC 000000H 000001H : FFFFFFH 24 Number of idle states inserted First byte transfers or remaining number of byte transfers Second byte transfers or remaining number of byte transfers : Byte transfer of 2 times or remaining number of byte transfers 105 CHAPTER 8 DMA FUNCTION 8.3.4 DMA channel control registers 0 through 3 (DCHC0 through DCHC3) These 16-bit registers control the DMA transfer operation modes of DMA channels 0 through 3. Figure 8-7. DMA Channel Control Registers 0 through 3 (DCHC0 through DCHC3) (1/3) Address of DCHC0: C000003CH Address of DCHC1: C000004CH Address of DCHC2: C000005CH Address of DCHC3: C000006CH 15 DCHC0 - 3 0 14 13 TTYP 12 11 TBT 10 9 SAD 8 7 DAD 6 5 DAL 4 DRL 3 TM 2 DS 1 0 EN Initial value: R/W: 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 14 - 12 Bit Name TTYP Transfer Type Description These bits specify the cause that starts DMA transfer. TTYP 0 0 0 0 1 1 1 1 11, 10 TBT 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Start cause Started by DMARQn signal: 2-cycle transfer Started by software: 2-cycle transfer Setting prohibited Setting prohibited Started by INTST signal: 2-cycle transfer Started by INTSR signal: 2-cycle transfer Started by INTCSI signal: 2-cycle transfer Started by INTCM4 signal: 2-cycle transfer Transfer Block Type These bits specify whether the address blocks at the transfer source and destination are in memory or I/O. TBT 0 0 1 1 0 1 0 1 Transfer block Memory to memory Memory to I/O I/O to memory Setting prohibited 9, 8 SAD Source Address Count Direction These bits specify the count direction of the transfer source address of DMA channel n (n = 0 to 3). SAD 0 0 1 1 0 1 0 1 Count direction Increment Decrement Fixed Setting prohibited 106 CHAPTER 8 DMA FUNCTION Figure 8-7. DMA Channel Control Registers 0 through 3 (DCHC0 through DCHC3) (2/3) Address of DCHC0: C000003CH Address of DCHC1: C000004CH Address of DCHC2: C000005CH Address of DCHC3: C000006CH 15 DCHC0 - 3 0 14 13 TTYP 12 11 TBT 10 9 SAD 8 7 DAD 6 5 DAL 4 DRL 3 TM 2 DS 1 0 EN Initial value: R/W: Bit 7, 6 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit Name DAD Destination Address Count Direction Description These bits specify the count direction of the transfer destination address of DMA channel n (n = 0 to 3). DAD 0 0 1 1 5 DAL 0 1 0 1 Count direction Increment Decrement Fixed Setting prohibited DMAAK Level This bit specifies the active level of the DMAAKn signal (n = 0 to 3). 0: Active low 1: Active high Caution The DMAAKn signal goes high from when the device has been reset until this register is set. 4 DRL DMARQ Level This bit specifies the level at which the DMARQn signal is detected (n = 0 to 3). 0: Detects low level 1: Detects high level 3 TM Transfer Mode This bits specifies a transfer mode during DMA transfer (n = 0 to 3). 0: Single transfer mode 1: Demand transfer mode Caution Select the signal transfer mode when DMA transfer is started by a request from the internal peripheral hardware. 2, 1 DS Data Size These bits specify the transfer size for DMA transfer. If the transfer destination is the I/O space, set the transfer data size greater than the data bus width (transfer destination) set by the DBC register (except when the address count is fixed (DAD bit = 10)). DS 0 0 1 1 0 1 0 1 Transfer data size Byte unit Half word (2 bytes) unit Word (4 bytes) unit Setting prohibited 107 CHAPTER 8 DMA FUNCTION Figure 8-7. DMA Channel Control Registers 0 through 3 (DCHC0 through DCHC3) (3/3) Address of DCHC0: C000003CH Address of DCHC1: C000004CH Address of DCHC2: C000005CH Address of DCHC3: C000006CH 15 DCHC0 - 3 0 14 13 TTYP 12 11 TBT 10 9 SAD 8 7 DAD 6 5 DAL 4 DRL 3 TM 2 DS 1 0 EN Initial value: R/W: 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 0 Bit Name EN Enable Description This bit enables or disables DMA transfer of DMA channel n (n = 0 to 3). It is reset when DMA transfer is completed by terminal count. To start DMA transfer, set the EN bit to 1, TCn bit of the DC register to 0, and MEN bit to 1 (n = 0 to 3). 0: Disables DMA transfer (reset) 1: Enables DMA transfer 108 CHAPTER 8 DMA FUNCTION 8.3.5 DMA control register (DC) This 16-bit register controls the DMA transfer operation mode. Figure 8-8. DMA Control Register (DC) Address: C000006EH 15 DC 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 TC3 6 TC2 5 TC1 4 TC0 3 0 2 0 1 0 0 MEN Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Bit 7-4 Bit Name TC3 - TC0 Terminal Count Channel3 - 0 Description These bits are status bits that indicate whether DMA transfer by DMA channel n has been completed (n = 0 to 3). They can be only read. These bits are set when DMA transfer has been completed by terminal count, and are reset when they are read. 0: DMA transfer not completed (reset) 1: DMA transfer completed 0 MEN Master Enable This bit enables or disables DMA transfer by all the DMA channels (n = 0 to 3). It is also reset by the NMI signal. To start DMA transfer, set the MEN bit to 1, TCn bit to 0, and EN bit of the DCHCn register to 1 (n = 0 to 3). To enable or disable transfer by each channel, use the EN bit of the DCHC0 through DCHC3 registers. Example To set the MEN bit to 1 only when DMA transfer is enabled, and to set the MEN bit to 1 during NMI processing only when the MEN bit is cleared by the NMI signal 0: Disables DMA transfer (reset) 1: Enables DMA transfer 109 CHAPTER 8 DMA FUNCTION 8.4 Transfer Mode 8.4.1 Single transfer mode In the single transfer mode, the DMAC releases the bus each time it has executed a transfer. If a DMA transfer request is issued after that, the DMAC executes a transfer once again. This is repeated until the terminal count is generated. If another DMA transfer request with a higher priority is issued while the DMAC has released the bus, the DMA request with the higher priority always takes precedence. Figures 8-9 and 8-10 show examples of single transfer. Figure 8-10 is an example where a DMA request with the higher priority is issued. In this example, DMA channel 0 is in the demand transfer mode and channel 1 is in the single transfer mode. Figure 8-9. Example of Single Transfer 1 DMARQ1 CPU DMA1 CPU DMA1 CPU DMA1 CPU CPU CPU CPU CPU CPU DMA1 CPU DMA1 CPU CPU CPU Terminal count of DMA channel 1 Figure 8-10. Example of Single Transfer 2 DMARQ0 DMARQ1 CPU DMA1 CPU DMA1 CPU DMA0 DMA0 DMA0 DMA0 DMA1 CPU DMA1 CPU DMA1 CPU CPU CPU CPU Terminal count of DMA channel 0 Terminal count of DMA channel 1 110 CHAPTER 8 DMA FUNCTION 8.4.2 Demand transfer mode In the demand transfer mode, the DMAC does not release the bus while DMA transfer requests are being issued. As long as DMA transfer requests are being issued, transfer continues until the terminal count is generated. If DMA transfer requests are stopped and then a request is issued again, transfer can be resumed. Figure 8-11 shows an example of demand transfer. This is an example where a DMA request with the higher priority is issued, and DMA channels 0 and 1 are in the demand transfer mode. Figure 8-11. Example of Demand Transfer DMARQ0 DMARQ1 CPU DMA1 DMA1 DMA1 DMA1 DMA0 DMA0 DMA0 DMA0 DMA1 DMA1 DMA1 DMA1 CPU CPU DMA1 DMA1 CPU Terminal count of DMA channel 0 8.5 DMA Transfer Type and Subject to Transfer 8.5.1 Two-cycle transfer The two-cycle transfer is to transfer data in two cycles, from the transfer source to the DMAC and from the DMAC to transfer destination. First cycle : Outputs transfer source address and reads data from transfer source to DMAC Second cycle: Outputs transfer destination address and writes data from DMAC to transfer destination. Figure 8-12 shows an example of 2-cycle transfer. 111 CHAPTER 8 DMA FUNCTION Figure 8-12. Two-Cycle Demand Transfer (external I/O to DRAM (on-page)) DMA state CLKOUT (output) DMARQ0 (input) (active level: H) DMAAK0 (output) (active level: L) Ti Ti T0 T0 T0 T1r T2r T2r T2r T1w T2w T3 Ti A1 - A23 (output) I/O address Note BCYST (output) RAS (output) L xxCAS (output) WE (output) IORD (output) D0 - D31 (I/O) Note DRAM column address Remarks 1. 2. 3. xxCAS: LLCAS, LUCAS, ULCAS, UUCAS The dotted lines indicate the high-impedance state. The arrows indicate the sampling timing. 8.5.2 Subject to transfer The relation between the transfer type and subject to transfer is shown below. Subject to DMA Transfer Between I/O (external or internal) and memory Between memory and memory Transfer Type 2-cycle 2-cycle Cautions 1. The DMAC cannot access the internal RAM. Use the IN.W/OUT.W instruction to access the internal I/O. 2. The DMAC cannot access the internal I/O in the CPU core. 3. Do not write anything to the DMAC register during DMA transfer. 4. If DMA transfer is executed (to write data) to the cacheable area, invalidate the cache as necessary because the values of the memory and cache differ. 112 CHAPTER 8 DMA FUNCTION 8.6 Priorities of DMA Channels The priorities of the DMA channels are fixed as follows: DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3 The DMA request is sampled only at the rising edge of the clock in the Ti state of the DMA state, and at the rising edge of the clock at which the BCYST signal is asserted active in write cycle (sampling in the write cycle is performed only during demand transfer). At this time, the priorities are valid, and DMA transfer with the higher priority is executed starting from the next transfer. 8.7 DMA Transfer Request The DMA transfer request is issued from three sources: external DMARQ pin, software, or internal peripheral hardware. These sources are specified by the DMA channel control register (DCHC). The DMAAK signal is output regardless of which of the three sources a DMA request has been issued. 8.7.1 Request from DMARQ pin The request from the DMARQ pin is sampled at the falling edge of the clock in the Ti state of the DMA state. This request must be continuously issued until the corresponding DMAAK signal is asserted active. If the DMARQ pin becomes active when the DMAC is in the Ti state, the DMAC enters the T0 state and starts DMA transfer. The request from the DMARQ pin is sampled in the demand transfer mode at the rising edge of the clock at which the BCYST signal is asserted active in the write cycle. If the next transfer is not executed in the demand transfer mode, check the BCYST signal in the T1r state, and then deassert the DMARQ signal inactive (because the request is sampled at the rising edge of the clock at which the BCYST signal is asserted active in the write cycle, process the request in the read cycle). When the DMARQ pin is asserted active, DMA transfer is started. However, if the DMARQ pin is left active, the next DMA transfer is started. When designing a system, allow enough time to assert the DMARQ pin active. The following describes the sampling timing of the DMARQ pin for the next DMA transfer in the transfer mode. (1) Two-cycle demand transfer The DMARQ pin is sampled with the timing <1> shown in Figure 8-13 in demand transfer. The DMARQ pin in the second DMA transfer cycle is sampled with the timing <2>. If the second DMA transfer cycle must not be generated, deassert the DMARQ pin inactive in the timing from <4> to <2>. The DMA transfer idle state is not set in the timing in Figure 8-13. When idle state is set, an idle state is inserted between the SRAM read and DRAM write (between Ts and Tc). 113 CHAPTER 8 DMA FUNCTION Figure 8-13. Two-Cycle Demand Transfer (16-bit SRAM to 32-bit DRAM, 32-bit transfer) First DMA transfer cycle Ti CLKOUT (output) <1> DMARQn (input) (active level: H) <4> DMAAKn (output) (active level: L) <2> <3> Ti T0 T0 T0 T0 Ta Ts Ta Ts Second DMA transfer cycle Ts Ta Ts Tc Tce Tc Tce Ta A1-A23 (output) SRAM L SRAM H DRAM CA SRAM L SRAM H DRAM CA BCYST (output) RAS (output) L XXCAS (output) WE (output) MRD (output) D0-D31 (input) Remarks 1. 2. 3. n = 0 to 3 xxCAS: LLCAS, LUCAS, ULCAS, UUCAS The dotted lines indicate the high-impedance state. 114 CHAPTER 8 DMA FUNCTION Figure 8-14. Two-Cycle Demand Transfer (32-bit DRAM to 16-bit SRAM, 32-bit transfer) First DMA transfer cycle Ti CLKOUT (output) <1> DMARQn (input) (active level: H) <4> DMAAKn (output) (active level: L) <2> <3> Ti T0 T0 T0 T0 Tc Tce Ta Ts Ta Ts Second DMA transfer cycle Tc Tce Ta Ts Ta Ts A1-A23 (output) DRAM CA SRAM L SRAM H DRAM CA SRAM L SRAM H BCYST (output) RAS (output) L XXCAS (output) WE (output) MRD (output) D0-D31 (input) CSm (SRAM) (output) Remarks 1. 2. 3. 4. n = 0 to 3 xxCAS: LLCAS, LUCAS, ULCAS, UUCAS m = 1 to 7 The dotted lines indicate the high-impedance state. 115 CHAPTER 8 DMA FUNCTION (2) Single transfer The DMARQ pin is sampled with the timing <1> in the single transfer shown in Figure 8-15. The state of the DMARQ pin is retained up to the timing <3>. The DMARQ pin is sampled in the second DMA transfer cycle with the timing <2>. If a second DMA transfer cycle must not be generated in single transfer, deassert the DMARQ pin inactive in the timing from <3> to <2>. Figure 8-15. Single Transfer (16-bit SRAM to 32-bit DRAM, 32-bit transfer) DMA transfer cycle Ti CLKOUT (output) <1> DMARQn (input) (active level: H) <3> DMAAKn (output) (active level: L) <2> Ti T0 T0 T0 T0 Ta Ts Ta Ts Tc Tce Ti Ti A1-A23 (output) SRAM L SRAM H DRAM CA BCYST (output) RAS (output) L XXCAS (output) WE (output) MRD (output) D0-D31 (input) Remarks 1. 2. 3. n = 0 to 3 xxCAS: LLCAS, LUCAS, ULCAS, UUCAS The dotted lines indicate the high-impedance state. 116 CHAPTER 8 DMA FUNCTION Figure 8-16. Single Transfer (8-bit I/O to 32-bit SRAM, 8-bit transfer) DMA transfer cycle Ti CLKOUT (output) <1> DMARQn (input) (active level: H) <3> DMAAKn (output) (active level: L) <2> Ti T0 T0 T0 T0 Ta Ts Ts Ts Ta Ts Ti Ti A1-A23 (output) I/O address SRAM address BCYST (output) CSm (I/O) (output) CSm (SRAM) (output) IORD (output) xxMWR (output) D0-D31 (input) READY (input) Remarks 1. 2. 3. 4. 5. n = 0 to 3 m = 1 to 7 xxMWR: LLMWR, LUMWR, ULMWR, UUMWR The arrows indicate the sampling timing. The dotted lines indicate the high-impedance state. 8.7.2 Request from software When a DMA request is issued from software and when the EN bit of the DCHC register is set to 1, DMA transfer is started. 117 CHAPTER 8 DMA FUNCTION 8.7.3 Request from internal peripheral hardware The following four types of transfer request signals (interrupt request signals) are issued from the internal peripheral hardware. * * * * Transmit end interrupt from UART (INTST) Receive end interrupt from UART (INTSR) Transmit/receive end interrupt from CSI (INTCSI) Compare register 4 (CM4) coincidence interrupt from RPU (INTCM4) Transfer is executed once each time a transfer request is issued from the internal peripheral hardware. Even if the next transfer request is issued before ongoing transfer is completed, that request is ignored. The transfer request from one internal peripheral hardware unit cannot be used with multiple channels. Use the single transfer mode. The transfer request from the internal peripheral hardware is generated even if it is masked by the interrupt request mask register (IMR). When an internal peripheral hardware interrupt request is used as a DMA transfer request signal, an interrupt request is generated. If an interrupt should not occur from the same internal peripheral when a transfer request from the internal peripheral hardware is used, mask the corresponding interrupt request by using the interrupt mask register. Caution Issue a transfer request from the internal peripheral hardware after setting of DMA transfer (including enabling transfer) has been completed. If a transfer request from the internal peripheral hardware is generated before DMA transfer is set, transfer is executed immediately after the setting of DMA transfer. Here are two examples of this. Example 1. To process data of CSI with two tasks (tasks 1 and 2) Task 1: Software transfer from CSI by interrupt servicing of CPU Task 2: DMA transfer from CSI If DMA transfer of task 2 is set after data has been received to CSI and the data of CSI has been received by task 1 (software transfer), the DMA transfer request by task 1 is retained. Consequently, DMA transfer is executed, even if data has not been received to CSI, as soon as DMA transfer of task 2 has been set. If starting DMA transfer from the DMARQ pin is set first and then the setting is changed to starting DMA transfer from the internal peripheral hardware, and if an interrupt occurs even once from the internal peripheral hardware, DMA transfer is started as soon as the setting has been changed to starting it from the internal peripheral hardware. Example 2. To execute DMA transfer by INTCM4 for a certain period while a timer (CM4) operates Because the transfer request by the timer interrupt is retained by the interrupt request register (IRR), DMA transfer is started as soon as DMA transfer has been enabled. 118 CHAPTER 8 DMA FUNCTION Figure 8-17. Example of Transfer on Request from Internal Peripheral Hardware Interrupt request signal CPU DMA CPU DMA CPU DMA CPU CPU CPU CPU CPU CPU DMA CPU DMA CPU CPU CPU DMA terminal count 8.8 DMA Transfer End Interrupt When DMA transfer is completed and the TCn bit of the DC register is set to 1, a DMA transfer end interrupt request is issued to the Interrupt controller (refer to Table 4-2. Interrupt List (Maskable Interrupts)). 8.8.1 TCn bit reference and DMA transfer end interrupt The DMAC of the V831 generates a DMA transfer end interrupt (INTDMA) and sets the bit of the channel corresponding to the TCn bit of the DMA control register (DC) to 1 when DMA transfer is completed. In a system where two or more DMA channels are used, the timing to read the TCn bit in the INTDMA handler and the timing to clear the interrupt latch of INTDMA must be carefully determined (n = 0 to 3). For example, when DMA transfer is executed by using two channels (channels 0 and 1), process the interrupt handler of INTDMA in the following sequence: <1> Clear the interrupt latch of the DMA transfer end interrupt (INTDMA). <2> Read the TCn bit of the DMA control register (DC). <3> Process transfer completion of all the DMA channels corresponding to the bit for which TCn is set. 119 CHAPTER 8 DMA FUNCTION Figure 8-18. Transfer End Processing of Channels 0 and 1 (a) End of transfer by channel 0 (b) End of transfer by channel 1 (1) (2) Channel 0 Channel 1 Time lapse To process transfer completion by INTDMA during period (1) Because the TCn bit of only channel 0 is set, the transfer completion processing of only channel 0 is performed. INTDMA occurs again in the timing when DMA transfer of channel 1 has been completed (b), and transfer completion processing of channel 1 is performed. To process DMA transfer completion for the first time during period (2) If the TCn bit is read during the period of <2>, transfer completion of both channels 0 and 1 is processed by the handler of INTDMA because both channels 0 and 1 are set. To process DMA transfer completion during period of (2), interrupts (a) and (b) occur. Because the interrupt request of interrupt (b) is already active in the timing of (a), the interrupt request is overwritten in the timing of (b), and the CPU cannot identify interrupt (b). Caution Read the TCn bit of the DC register after clearing the interrupt latch of INTDMA. If this sequence is reversed, and if transfer by channel 1 has been completed immediately after the DC register has been read, the interrupt of channel 1 does not occur and completion processing of channel 1 cannot be performed because the interrupt latch of INTDMA is cleared. 120 CHAPTER 8 DMA FUNCTION 8.9 DMA Transfer End Output The TC signals become active for the duration of one clock at the clock next to the one at which the BCYST signal is asserted active in the write cycle in which DMA transfer is completed (the TC signal is output at the second clock of the write cycle when the internal peripheral I/O is written). Figure 8-19 shows the output timing of the TC signal when transfer is executed from an SRAM area to another SRAM area. The TC signal is output by ORing the DMA transfer end outputs of channels 0 through 3. The DMA transfer end outputs of channels 0 through 3 can be created by ANDing the DMAAK0 through DMAAK3 signals with an external circuit. The function of the pin multiplexed with the TC/REFRQ pin is selected by using the RFTC bit of the RFC register. Because the REFRQ pin is selected (RFTC bit = 1) as default assumption, the REFRQ signal is output. Figure 8-19. DMA Transfer End Output Timing Read (WSn = 0) Ta CLKOUT (output) Ts Ta Write (WSn = 1) Ts Ts Read (WSn = 0) Ta Ts Ta Write (WSn = 1) Ts Ts CS1 - CS7 (output) A1 - A23 (output) D0 - D31 (I/O) MRD (output) xxMWR (output) BCYST (output) READY (output) DMAAK0 (output) IORD (output) H IOWR (output) H TC (output) Remarks 1. 2. 3. xxMWR: LLMWR, LUMWR, ULMWR, UUMWR The dotted lines indicate the high-impedance state The arrows indicate the sampling timing. 121 CHAPTER 8 DMA FUNCTION 8.10 Abort 8.10.1 Aborting by NMI signal DMA transfer under execution can be forcibly stopped by inputting the NMI signal (in this case, the transfer is aborted after the write cycle has been completed). At this time, the DMAC clears the MEN bit of the DC register to disable DMA transfer. If the MEN bit is set to 1 again, the DMA transfer can be resumed from where it has been aborted. If the NMI signal is input while the non-maskable interrupt is serviced, the CPU core keeps this interrupt pending. However, a request to abort DMA transfer is not kept pending. Therefore, even if the NMI signal is input while the MEN bit is 0, the request to abort DMA transfer is ignored. The MEN bit is not cleared to 0 even if the NMI signal is input in the STOP mode (while the bus clock is stopped). Even if the bus clock output is released, the MEN bit is cleared to 0 if the NMI signal is active. 8.10.2 Temporary stop by HLDRQ signal or refresh DMA transfer can be temporarily stopped (after the write cycle has been completed) by inputting the HLDRQ signal or issuing a DRAM refresh request (refer to 5.9 Bus Arbitration). If the DMA request is active when a bus master having a priority higher than the DMAC has released the bus, the DMA transfer is resumed. The DMAAK signal is deasserted inactive while the DMA transfer is temporarily stopped. 122 CHAPTER 8 DMA FUNCTION 8.11 Bus Sizing during DMA Transfer The V831 has a bus sizing function that selects a bus width from 32 bits or 16 bits. To access 32-bit data via the 16-bit data bus, the data is accessed two times. These two accesses are made in the burst cycle. Figure 8-20 shows an example of 32-bit (word) demand transfer where the data at the transfer source is 16 bits long (I/O) and the transfer destination data bus width is 32 bits (DRAM). Figure 8-20. 16- to 32-Bit Data Bus Width (32-bit transfer bus sizing) Ta CLKOUT (output) Tss Twa Ts Tc Tce Ta Tss Twa Ts Tc Tce DMAAK0 (output) A1 - A23 (output) I/O I/O DRAM CA I/O I/O DRAM CA BCYST (output) RAS (output) L xxCAS (output) WE (output) IORD (output) D0 - D31 (I/O) Remarks 1. 2. xxCAS: LLCAS, LUCAS, ULCAS, UUCAS The dotted lines indicate the high-impedance state. Figure 8-21 shows an example of 32-bit (word) demand transfer where the data at the transfer source is 16 bits long (I/O) and the data bus width at the transfer destination is 16 bits (DRAM). If the DRAM write cycle is used as burst cycle as a result of bus sizing, the output timing of the TC signal is the Twc state. In a cycle other than the DRAM write cycle, the TC signal is output in the first write cycle. 123 CHAPTER 8 DMA FUNCTION Figure 8-21. 16- to 16-Bit Data Bus Width (32-bit transfer bus sizing) Ta CLKOUT (output) Tss Twa Ts Tc Twc Tce Ta Tss Twa Ts Tc Twc Tce DMAAK0 (output) A1-A23 (output) I/O I/O CA1 CA2 I/O I/O CA1 CA2 BCYST (output) RAS (output) L xxCAS (output) WE (output) IORD (output) D0 - D31 (I/O) TC (output) Remarks 1. 2. xxCAS: LLCAS, LUCAS, ULCAS, UUCAS The dotted lines indicate the high-impedance state. 124 CHAPTER 9 SERIAL INTERFACE FUNCTION The V831 has two transmit/receive channels to provide serial interface functions. As the interfacing modes, the following two types are available with each type provided by one channel. * * Asynchronous serial interface: UART (Universal Asynchronous Receiver/Transmitter) Clocked serial interface : CSI One channel of BRG (baud rate generator) is provided and can be used exclusively with UART and CSI. 9.1 Asynchronous Serial Interface (UART) 9.1.1 General The UART of the V831 has the following features: * * Transmit buffer register is not provided. A dedicated baud rate generator is provided so that any baud rate can be set. (1) Deletion of transmit buffer The conventional UART has a transmit buffer and a receive buffer at both the transimit and receive sides. The V831 omits the transmit buffer for the purpose of mitigating the hardware, and starts transmission processing by transferring data to the transmit shift register. Therefore, the transmit enable control function for the transmit buffer and transmission processing control function by the CTS (serial transmission control) pin are also omitted, and these controls should be implemented by software controlling interrupts. A receive buffer is provided as in the conventional processor. (2) On-chip dedicated baud rate generator The V831 has one channel of dedicated baud rate generator that generates serial clocks and can set an accurate serial transfer rate. 125 CHAPTER 9 SERIAL INTERFACE FUNCTION 9.1.2 Features * * Full duplex communication. Receive buffer (RXB) is provided (transmit buffer (TXB) is not provided). Two-pin configuration (The UART of the V831 does not have the SCLK and CTS pins.) * * TXD: Transmit data output pin RXD: Receive data input pin * * * Transfer rate: 150 bps to 76800 bps (bus clock: 33 MHz, with BRG) Baud rate generator Serial clock source can be selected from band rate generator output or bus clock () Receive error detection function * * * Parity error Framing error Overrun error Receive error interrupt (INTSER) The interrupt is generated by ORing three types of receive errors (for the details of the errors, refer to 9.1.4 (3) Asynchronous serial interface status register (ASIS0)). * Three interrupt sources * * Receive end interrupt (INTSR) The receive end interrupt request is generated after completion of receive data transfer from the shift register to the receive buffer in the reception enabled status. * Transmit end interrupt (INTST) The transmit end interrupt is generated after completion of serial transfer of transmit data (9, 8, or 7 bits) from the shift register. The character length of the transmit/receive data is specified by the ASIM00 and ASIM01 registers. * * * Character length : 7 or 8 bits : 9 bits (with extension bit appended) Parity function : Odd, even, 0, or none Transmit stop bit : 1 or 2 bits 126 CHAPTER 9 SERIAL INTERFACE FUNCTION 9.1.3 Configuration Figure 9-1. Block Diagram of UART Internal peripheral I/O bus 16/8 8 RXB0 Receive buffer RXB0L 8 16/8 Mode register ASIM00 ASIM01 RXD Receive shift register Status register ASIS0 Transmit shift register TXS0 TXS0L TXD Receive control parity check INTSER Transmit control parity append INTST INTSR 1/16 1/16 1/2 SEL Baud rate generator Remark = bus clock (33 MHz to 16.7 MHz) 127 CHAPTER 9 SERIAL INTERFACE FUNCTION 9.1.4 Mode registers and control registers (1) Asynchronous serial interface mode register 00 (ASIM00) This register specifies the transfer mode of the UART. It can be read or written in 8-bit units. Caution If the value of ASIM00 is changed during transmission or reception by the UART, the operation is not guaranteed. Figure 9-2. Asynchronous Serial Interface Mode Register 00 (ASIM00) (1/2) Address: C0000090H 7 ASIM00 1 6 5 4 3 2 SL0 1 0 0 SCLS0 RXE0 PS01 PS00 CL0 Initial value: R/W: Bit 6 Bit Name RXE0 Receive Enable 1 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W Description Enables or disables reception. 0: Disables reception 1: Enables reception The receive shift register does not detect the start bit when reception is disabled. The shift in processing and transfer to the receive buffer are not performed, and the contents of the receive buffer are retained. While reception is enabled, the receive shift operation is started in synchronization with detection of the start bit. When reception of one frame has been completed, the contents of the receive shift register are transferred to the receive buffer. In addition, the receive end interrupt (INTSR0) is generated in synchronization with transfer to the receive buffer. 5, 4 PS01, PS00 Parity Select Specifies a parity bit. PS01 PS00 0 0 0 1 No parity Specifies 0 parity Transmission side Transmits data with 0 parity bit Reception side Does not generate parity error on reception 1 1 3 CL0 0 1 Specifies odd parity Specifies even parity Operation Character Length Specifies the character length of one frame. 0: 7 bits 1: 8 bits 2 SL0 Stop Bit Length Specifies the stop bit. 0: 1 bit 1: 2 bits 128 CHAPTER 9 SERIAL INTERFACE FUNCTION Figure 9-2. Asynchronous Serial Interface Mode Register 00 (ASIM00) (2/2) Address: C0000090H 7 ASIM00 1 6 5 4 3 2 SL0 1 0 0 SCLS0 RXE0 PS01 PS00 CL0 Initial value: R/W: 1 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W Bit 0 Bit Name SCLS0 Serial Clock Source Specifies a serial clock. 0: Baud rate generator output 1: (bus clock) Description The serial clock is generated by dividing the serial clock source specified by the SCLS0 bit of the ASIM00 register by two. The clock resulting from dividing the serial clock by 16 is used as the baud rate clock of the UART. * When SCLS0 = 1 (bus clock) is selected as the serial clock source. The baud rate can be calculated by the following expression because a sampling rate of x 16 is used. Baud rate = /2/16 (bps) The value of the baud rate when a representative clock is used based on the above expression is shown below. Baud rate (bps) 33 MHz 1031 K 25 MHz 781 K 20 MHz 625 K 16 MHz 500 K * When SCLS0 = 0 The baud rate generator output is selected as the serial clock source. For details of the baud rate generator, refer to 9.3 Baud Rate Generator. 129 CHAPTER 9 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface mode register 01 (ASIM01) This register specifies the transfer mode of the UART. It can be read or written in 8-bit units. Figure 9-3. Asynchronous Serial Interface Mode Register 01 (ASIM01) Address: C0000092H 7 ASIM01 0 6 0 5 0 4 0 3 0 2 0 1 0 0 ESB0 Initial value: R/W: Bit 0 Bit Name ESB0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W Description Extended Bit Select Specifies operation without parity (PS01, PS00 = 00). 0: Disables extended bit operation 1: Enables extended bit operation When the extended bit is specified, 1 data bit is appended to the high-order nibble of the 8bit transmit/receive data, extending the number of bits to 9 bits. This function is valid only when the operation without parity is specified by the ASIM00 register. When 0 parity, or odd or even parity is specified, the specification by the ESB0 bit is invalid, and the extended bit cannot be appended. 130 CHAPTER 9 SERIAL INTERFACE FUNCTION (3) Asynchronous serial interface status register (ASIS0) This register consists of 3-bit error flags indicating an error status on completion of reception of the UART, and transmit status flags. It can be only read in 8-bit units. If a receive error occurs, read this register, and then read the receive buffer RXB0 or RXB0L, and clear the error flag to 0. The status flag indicating a receive error always indicates the latest error. If the same error has occurred several times before the receive data is read, only the status of the error that occurred last is retained. Figure 9-4. Asynchronous Serial Interface Status Register (ASIS0) Address: C0000094H 7 ASIS0 SOT0 6 0 5 0 4 0 3 0 2 PE0 1 0 FE0 OVE0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bit 7 Bit Name SOT0 Status Of Transmission Description Status flag indicating the transmission operation status. 1: Transmit start timing 0: Transmit end timing 2 PE0 Parity Error Status flag indicating parity error. 1: Transmit parity and receive parity do not coincide. 0: Data is read from receive buffer. 1 FE0 Framing Error Status flag indicating framing error. 1: Stop bit is not detected. 0: Data is read from receive buffer. 0 OVE0 Overrun Error Status flag indicating overrun error. 1: UART completes next reception before it receives data from receive buffer. 0: Receive data is read from receive buffer. Because the contents of the receive shift register are transferred to the receive buffer each time one frame has been received, the next data is written over the receive buffer and the previous receive data is not retained if an overrun error occurs. 131 CHAPTER 9 SERIAL INTERFACE FUNCTION (4) Receive buffer (RXB0, RXB0L) RXB0 is a 9-bit buffer register and its high-order bits contain 0 when a 7- or 8-bit character is received. To access this register in half word units (16 bits), specify RXB0. To access it in byte units, specify RXB0L. The receive buffer register can be only read. While reception is enabled, the receive data is transferred from the receive shift register to the receive buffer in synchronization with the end of shift in processing of one frame. When the data has been transferred to the receive buffer, the reception end interrupt request (INTSR) is generated. While reception is disabled, the data is not transferred to the receive buffer even after the shift in processing of one frame has been completed, and the contents of the receive buffer are retained. Nor is the reception end interrupt request (INTSR) generated. RXEB0 is an extended bit. The extended bit is stored to the RXEB0 bit when the extended bit operation is enabled by the ASIM01 register. When the extended bit operation is disabled, 0 is stored to this bit. Figure 9-5. Receive Buffer (RXB0, RXB0L) Address: C0000098H 15 RXB0 0 14 0 13 0 12 0 11 0 10 0 9 0 8 7 6 5 4 3 2 1 0 RXEB0 RXB07 RXB06 RXB05 RXB04 RXB03 RXB02 RXB01 RXB00 Initial value: R/W: - R - R - R - R - R - R - R - R - R - R - R - R - R - R - R - R Address: C000009AH 7 RXB0L 6 5 4 3 2 1 0 RXB07 RXB06 RXB05 RXB04 RXB03 RXB02 RXB01 RXB00 Initial value: R/W: - R - R - R - R - R - R - R - R Bit 8 Bit Name RXEB0 Receive Extended Buffer Description Extended bit used when 9-bit character is received. This bit is 0 when 7- or 8-bit character is received. 7-0 RXB0n (n = 7 - 0) Receive Buffer Stores receive data. RXB07 is 0 when 7-bit character is received. 132 CHAPTER 9 SERIAL INTERFACE FUNCTION (5) Transmit shift register (TXS0, TXS0L) TXS0 is a 9-bit shift register for transmit processing. By writing data to this register, the transmit operation is started. Because the UART of the V831 does not have a transmit buffer, an interrupt request is not generated on completion of transmission (completion of transfer to the buffer), but a transmit end interrupt request (INTST) occurs in synchronization with completion of one frame, including the data of TXS0. To access this register in half word units (16 bits), specify TXS0. To access it in byte units, specify TXS0L. TXED0 is an extended bit. The extended bit is stored to the TXED0 bit when the extended bit operation is enabled by the ASIM01 register. When the extended bit operation is disabled, 0 is stored to this bit. Figure 9-6. Transmit Shift Register (TXS0, TXS0L) Address: C000009CH 15 TXS0 0 14 0 13 0 12 0 11 0 10 0 9 0 8 7 6 5 4 3 2 1 0 TXED0 TXS07 TXS06 TXS05 TXS04 TXS03 TXS02 TXS01 TXS00 Initial value: R/W: - W - W - W - W - W - W - W - W - W - W - W - W - W - W - W - W Address: C000009EH 7 TXS0L 6 5 4 3 2 1 0 TXS07 TXS06 TXS05 TXS04 TXS03 TXS02 TXS01 TXS00 Initial value: R/W: - W - W - W - W - W - W - W - W Bit 8 Bit Name TXED0 Transmit Extended Data Description Extended bit when 9-bit character is transmitted 7-0 TXS0n (n = 7 - 0) Transmit Shifter Writes transmit data 133 CHAPTER 9 SERIAL INTERFACE FUNCTION 9.1.5 Interrupt requests The UART generates the following three types of interrupt requests. (1) Receive error interrupt (INTSER) A receive error interrupt request is generated by ORing the three types of receive errors while reception is enabled (refer to Figure 9-4 Asynchronous Serial Interface Status Register (ASIS0)). The receive error interrupt request is not generated while reception is disabled. (2) Receive end interrupt (INTSR) The receive end interrupt is generated when data is shifted in the receive shift register and transferred to the receive buffer while reception is enabled. The receive end interrupt request also is generated if a receive error occurs. The receive end interrupt request is not generated while reception is disabled. (3) Transmit end interrupt (INTST) The UART of the V831 generates the transmit end interrupt request if transmit data of one frame including a 7-, 8-, or 9-bit character is shifted out from the transmit shift register because it does not have a transmit buffer. The transmit end interrupt request is output when transmission of the last bit of the transmit data is started. DMA transfer can be executed by using the transmit end interrupt and receive end interrupt (refer to CHAPTER 8 DMA FUNCTION). 134 CHAPTER 9 SERIAL INTERFACE FUNCTION 9.1.6 Basic operation (1) Transmission (a) Transmission enabled status The UART is always in the transmission enabled status. Because the UART of the V831 does not have a CTS (serial transmission control) input pin, use a general-purpose input port to check whether the other party is in the receive enabled status. (b) Starting transmit operation The transmit operation is started when data is written to the transmit shift register (TXS0, TXS0L). (c) Format of transmit data Figure 9-7 shows the format of the transmit data. One frame of the data consists of a start bit, character bits, a parity bit, and stop bits. Figure 9-7. Transmit Data Format of UART 1 frame Data ST D0 D1 D2 D3 D4 D5 D6 D7 P STP : Start bit (1 bit) ST D0 - D7: Character bit (7 or 8 bits) : Parity, extended bit (odd parity, even parity, 0 parity, no parity, or extended bit) P STP : Stop bit (1 or 2 bits) (d) Transmit interrupt request The transmit end interrupt request is generated when one frame of data has been transmitted. Caution The empty status of TXS0 does not cause the transmit end interrupt. the transmit end interrupt does not occur even if TXS0 is empty after reset. (2) Reception (a) Reception enabled status The receive operation is enabled when the RXE0 bit of the ASIM00 register is set to 1. * RXE0 = 1 (reception enabled status) * RXE0 = 0 (reception disabled status) The transmit end interrupt is caused to be generated by completion of transmission of one frame. Therefore, 135 CHAPTER 9 SERIAL INTERFACE FUNCTION In the reception disabled status, the reception hardware stands by in the initial status. At this time, the receive end interrupt or receive error interrupt does not occur, and the contents of the receive buffer are retained. (b) Starting receive operation The receive operation is started when the start bit is detected. The RXD pin is sampled by the bus clock from the baud rate generator or serial clock. The RXD pin is sampled again eight serial clocks after the falling edge of the RXD pin has been detected. If the RXD pin is low, it is recognized as the start bit. Then the receive processing operation is started and the RXD pin input is sampled in units of 16 serial clocks. If a high level of the RXD pin is detected eight serial clocks after the falling edge of the RXD pin has been detected, this falling edge is not recognized as the start bit. The serial clock counter for sample timing generation is initialized and stopped, and waits for input of the next falling edge. (c) Receive end interrupt request When one frame of data has been received while reception is enabled (RXE0 = 1), the receive data in the shift register is transferred to RXB0, and the receive end interrupt request is generated. The receive end interrupt request is not generated while reception is disabled (RXE0 = 0). (d) Receive error flag The three error flags (0 through 2 bits of ASIS0 register), parity error, framing error, and overrun error flags, are affected in synchronization with the receive operation. The receive error interrupt is generated as a result of ORing these three error flags. 136 CHAPTER 9 SERIAL INTERFACE FUNCTION 9.2 Clocked Serial Interface (CSI) 9.2.1 Features z High-speed transfer: 8.25 Mbps MAX. (bus clock: 33 MHz) z Half duplex communication for transmission/reception (buffer is not provided) z Character length: 8 bits z External or internal clock selectable 9.2.2 Configuration Figure 9-8. Block Diagram of CSI Internal peripheral I/O bus 8 8 CSIM0 Mode register SIO0 SO latch Shift register D Q SI SO SCLK Serial clock control circuit SEL 1/2 Baud rate generator SEL 1/2, 1/4, 1/8, 1/16, 1/32 prescaler Serial clock counter Interrupt control circuit INTCSI Remark = bus clock (33 MHz to 16.7 MHz) 137 CHAPTER 9 SERIAL INTERFACE FUNCTION 9.2.3 Mode registers and control registers (1) Clocked serial interface mode register 0 (CSIM0) This register specifies the basic operation mode of the CSI. It can be read or written in 8-bit units (however, CSOT0 (bit 5) can be only read). Figure 9-9. Clocked Serial Interface Mode Register 0 (CSIM0) (1/2) Address: C00000A0H 7 6 5 4 3 0 2 1 0 CSIM0 CTXE0 CRXE0 CSOT0 MOD0 CLS02 CLS01 CLS00 Initial value: R/W: 0 R/W 0 R/W 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 7 Bit Name CTXE0 CSI Transmit Enable Enables or disables transmission. 0: Disables transmission. 1: Enables transmission. Description The output buffer of the SO pin goes into a high-impedance state when CTXE0 = 0. 6 CRXE0 CSI Receive Enable Enables or disables reception. 0: Disables reception. 1: Enables reception. If the serial clock is input when transmission is enabled (CTXE0 = 1) and reception is disabled, 0 is input to the shift register. 5 CSOT0 CSI Status Of Transmission Indicates that transmission is in progress. 0: End of transmission (write to SIO0 register) 1: Transmission in progress (INTCSI occurs) While transmission is in progress (CSOT0 = 1), the next transmit or receive operation is not started. 4 MOD0 Mode Specifies the first bit. 0: MSB first 1: LSB first 138 CHAPTER 9 SERIAL INTERFACE FUNCTION Figure 9-9. Clocked Serial Interface Mode Register 0 (CSIM0) (2/2) Address: C00000A0H 7 6 5 4 3 0 2 1 0 CSIM0 CTXE0 CRXE0 CSOT0 MOD0 CLS02 CLS01 CLS00 Initial value: R/W: 0 R/W 0 R/W 0 R 0 R/W 0 R 0 R/W 0 R/W 0 R/W Bit 2-0 Bit Name CLS02 CLS00 Clock Source Specifies a serial clock. CLS02 CLS01 CLS00 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 External clock Internal clock Description Specifies serial clock Note 1 SCLK pin Input Specified by BPRM0 register Output Output Output Output Output Output Reserved (setting prohibited) /4Note 2 /8Note 2 /16Note 2 /32 Note 2 /64Note 2 Notes1. For the setting of the BPRM0 register, refer to 9.3 Baud Rate Generator. 2. /4, /8, /16, /32, and /64 are divided signals. = bus clock (16 MHz to 33 MHz) (2) Serial I/O shift register 0 (SIO0) This register converts parallel data into serial data, or vice versa. It performs shift operation when CTXE0 = 1 or CRXE0 = 1. This register can be read or written in 8-bit units. Figure 9-10. Serial I/O Shift Register 0 (SIO0) Address: C00000A2H 7 6 5 4 3 2 1 0 SIO0 SIO07 SIO06 SIO05 SIO04 SIO03 SIO02 SIO01 SIO00 Initial value: R/W: - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W Bit 7-0 Bit Name SIO07 - SIO00 Serial I/O Description Data is shifted in (received) or shifted out (transmitted) from the MSB or LSB. 139 CHAPTER 9 SERIAL INTERFACE FUNCTION 9.2.4 Pin function The clocked serial interface (CSI) uses the following pins. These pins are multiplexed with an I/O port. Because the I/O port is selected in the initial status, set the PC2 through PC0 bits of the port control mode register (PC) to use the CSI (refer to 11.2.3 Port control mode register (PC)). * * * SO SI : Serial data output pin : Serial data input pin SCLK: Serial clock I/O pin (Select the mode of this pin by using the CSIM0 register.) 9.2.5 Basic operation (1) Transfer format The V831 performs interfacing by using one clock line and two data lines. Serial transfer is started when an instruction that writes transfer data to the SIO0 register is executed. During transmission, the data is output from the SO pin in synchronization with the falling of the SCLK signal. During reception, the input data of the SI pin is latched in synchronization with the rising of the SCLK pin. The SCLK signal is stopped when the serial clock counter overflows (at the rising of the eighth count), and an interrupt request signal (INTCSI) is generated. Figure 9-11. CSI Transfer Timing SCLK (output) 1 2 3 4 5 6 7 8 SI (input) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CSOT0 flag INTCSI End of serial transmission/reception. Interrupt request occurs. Transfer started in synchronization with falling of SCLK Execution of write instruction to SIO0 140 CHAPTER 9 SERIAL INTERFACE FUNCTION (2) Enabling transmission/reception Because the CSI of the V831 has only one 8-bit shift register and does not have a buffer, transmission and reception are performed simultaneously. (a) Transmission/reception enabling condition Transmission is enabled when CTXE0 = 1. Reception is enabled when CRXE0 = 1. Transmission and reception are enabled when CTXE0 = CRXE0 = 1. (i) Disabling SIO output by CTXE0 The serial output goes into a high-impedance state when CTXE0 = 1. The data of the shift register is output when CTXE0 = 1. (ii) Disabling SIO input by CRXE0 The shift register input is 0 when CRXE0 = 0. Serial data is input to the shift register when CRXE0 = 1. (iii) To check transmit data When the interface is used as a two-wire interface using the SI and SO signals, the interface receives transmit data by itself, and sets CTXE0 and CRXE0 to 1 to check that a bus conflict does not occur. (b) Starting transmission/reception Transmission or reception is started by reading/writing the shift register. When the transmit enable bit (CTXE0) and receive enable bit (CRXE0) are set as follows, starting transmission or reception is controlled. Table 9-1. Start Condition CTXE0 0 0 1 1 0 CRXE0 0 1 0 1 0 1 Start Condition Does not start Reads shift register Writes shift register Writes shift register Rewrites CRXE0 bit Transfer is not started even if CTXE0 is set to 1 after the shift register has been written when CTXE0 is 0. When the CRXE0 bit is set from 0 to 1 when CTXE0 is 0, the serial clock is generated and reception is started. The transmit or receive operation is not started when the CSOT0 bit of the CSIM0 register is 1 (transfer is in progress). 141 CHAPTER 9 SERIAL INTERFACE FUNCTION Caution When an external clock is used as the serial clock, and if the serial clock input from an external source is stopped before transfer or reception of data has been completed, the CSI of the V831 assumes the next serial clock to be the continuation of the aborted data (serial clock counter is not cleared). To stop and redo transfer or reception of such data, initialize the CSI in the following sequence: * * * Clear the CTXE and CRXE bits (temporarily stop transfer/reception). Set the CTXE and CRXE bits (enable transfer/reception again). To only transfer or receive data, clear and set the corresponding disable/enable bit. 9.3 Baud Rate Generator 9.3.1 Configuration and function The serial interface can use the serial clock output by the baud rate generator or the divided value of (bus clock) as a baud rate. The serial clock source is specified by the following registers. * * In the case of UART: Specified by the SCLS0 bit of the ASIM00 register (refer to Figure 9-2). In the case of CSI : Specified by the CLS02 through CLS00 bits of the CSIM0 register (refer to Figure 9-9). When the baud rate generator output is specified, the baud rate generator (BRG) is selected as the clock source. The baud rate generator is shared by the UART and CSI. Figure 9-12. Block Configuration of Baud Rate Generator (BRG) Internal peripheral I/O bus BRG0 Compare register BRCE0 BPR00 - 02 BPRM0 Serial interface (UART/CSI) TMBRG0 Internal timer Prescaler 1/2 Remark = bus clock (33 MHz to 16.7 MHz) 142 CHAPTER 9 SERIAL INTERFACE FUNCTION The baud rate generator consists of an 8-bit timer (TMBRG0) that generates a shift clock for transmission/reception, a compare register (BRG0), mode register (BPRM0), and prescaler. (1) Input clock The bus clock () is input to the BRG. (2) Setting of BRG (a) UART When the baud rate generator is used with the UART, the actual baud rate is calculated by the following expression because a sampling rate of x 16 is used. Baud rate = where, n 2 x m x 2 x 16 x 2 [bps] = Bus clock frequency [Hz] m = Set value of BRG0 register (1 m 256 Note ) n = Set value of prescaler (BPR00 through BPR02 of BPRM0 register) (n = 0, 1, 2, 3, or 4) Note (b) CSI When the baud rate generator is used with the CSI, the actual baud rate is calculated by the following expression. Baud rate = where, The value of m = 256 is set by writing 0 to the BRG0 register. n 2xmx2 x2 [bps] = Bus clock frequency [Hz] m = Set value of BRG0 register (1 m 256 Note ) n = Set value of prescaler (BPR00 through BPR02 of BPRM0 register) (n = 0, 1, 2, 3, or 4) Note The value of m = 256 is set by writing 0 to the BRG0 register. Table 9-2 shows the set values of the baud rate generator when the representative clocks are used. 143 CHAPTER 9 SERIAL INTERFACE FUNCTION Table 9-2. BRG Setting Data Baud Rate [bps] UART 110 150 300 600 1200 2400 4800 9600 10400 19200 38400 CSI 1760 2400 4800 9600 19200 38400 76800 153600 166400 307200 614400 BPR - 4 3 2 1 0 0 0 0 0 0 0 0 = 33 MHz BRG0 - 215 215 215 215 215 107 54 50 27 13 7 3 Error - 0.07% 0.07% 0.07% 0.07% 0.07% 0.39% 0.54% 0.84% 0.54% 3.29% 4.09% Note = 25 MHz BPR 4 4 3 2 1 0 0 0 0 0 0 0 0 BRG0 222 163 163 163 163 163 81 41 38 20 10 5 2 Error 0.02% 0.15% 0.15% 0.15% 0.15% 0.15% 0.47% 0.76% 1.16% 1.73% 1.73% 1.73% 27.2% BPR 4 4 3 2 1 0 0 0 0 0 0 0 0 = 20 MHz BRG0 178 130 130 130 130 130 65 33 30 16 8 4 2 Error 0.25% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 1.36% 0.16% 1.73% 1.73% 1.73% 1.73% BPR 4 3 2 1 0 0 0 0 0 0 0 - - = 16 MHz BRG0 142 208 208 208 208 104 52 26 24 13 7 - - Error 0.03% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% Note 6.99% - - 76800 1228800 153600 2457600 11.9% Note This setting cannot be made because the error rate is too high. Remark BPR = BPR00 through BPR02 bits of BPRM0 register 144 CHAPTER 9 SERIAL INTERFACE FUNCTION (3) Error rate of baud rate generator The error rate of the baud rate generator can be calculated by the following expression. Error [%] = Actual baud rate (baud rate including error) Desired baud rate (normal baud rate) - 1 x 100 Example ( ( 9520 - 1) x 100 = -0.833 [%] 9600 5000 - 1) x 100 = +4.167 [%] 4800 (4) Permissible error range of baud rate generator The permissible range of the baud rate generator depends on the number of bits of one frame. Basically, the permissible limit is a baud rate error of 5 % and a sampling timing of 4.5 % at 16 bits. The actual permissible limit, however, is a baud rate error of 2.3 %, considering that both the transmission and reception sides include an error. 9.3.2 Baud rate generator compare register (BRG0) This is an 8-bit compare register that sets the timer/count value of the baud rate generator and can be read/written in 8-bit units. The internal timer (TMBRG0) is cleared by writing to the BRG0 register. rewritten by software during transmission/reception. Figure 9-13. Baud Rate Generator Compare Register (BRG0) Address: C00000B0H 7 6 5 4 3 2 1 0 Therefore, this register cannot be BRG0 BRG07 BRG06 BRG05 BRG04 BRG03 BRG02 BRG01 BRG00 Initial value: R/W: - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W 145 CHAPTER 9 SERIAL INTERFACE FUNCTION 9.3.3 Baud rate generator prescaler mode register (BPRM0) This register controls the timer/count operation of the dedicated baud rate generator and selects a count clock. It can be read or written in 8-bit units. Figure 9-14. Baud Rate Generator Prescaler Mode Register (BPRM0) Address: C00000B2H 7 BPRM0 BRCE0 6 0 5 0 4 0 3 0 2 1 0 BPR02 BPR01 BPR00 Initial value: R/W: 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 7 Bit Name BRCE0 Baud Rate Generator Count Enable Controls the count operation of BRG. 0: Clears and stops count operation. 1: Enables count operation Description 2-0 BPR02 - BPR00 Baud Rate Generator Prescaler Specifies a count clock to be input to TMBRG0. BPR02 0 0 0 0 1 Remark BPR01 0 0 1 1 x BPR00 0 1 0 1 x Operation /2 (n = 0) /4 (n = 1) /8 (n = 2) /16 (n = 3) /32 (n = 4) n: Prescaler set value, : Bus clock Caution The count clock cannot be changed during transmission/reception. 146 CHAPTER 10 TIMER/COUNTER FUNCTION 10.1 Features * Measures pulse interval and frequency and outputs programmable pulse * * 16-bit measurement Can generate pulses of various shapes (interval pulse, one-shot pulse) 16-bit timer/event counter Source of count clock Count clear pin Interrupt source External pulse output 16-bit interval timer Count clock selected by dividing system clock Compare register: x 1 Interrupt source : 1 type : 2 types (selected by dividing system clock, external pulse input) : TCLR : 5 types : 2 pins Capture/compare register: x 4 * Timer 1 * * * * * * * Timer 4 * * * * 147 CHAPTER 10 TIMER/COUNTER FUNCTION 10.2 Configuration (1) Timer 1 (16-bit timer/event counter) Figure 10-1. Block Configuration of Timer 1 Edge detection Clear & start /2 /4 m m m/4 m/16 Note 1 TCLR1 TM1 (16 bits) TI Note 2 INTOV1 Edge detection INTCC10 INTCC11 INTP10 INTP11 INTP12 INTP13 Edge detection Edge detection Edge detection Edge detection CC10 CC11 CC12 CC13 S R S R Note 3 Note 3 Q TO10 Q Q TO11 Q INTCC12 INTCC13 Notes 1. Internal count clock 2. External count clock (TI: 4.125 MHz max.) 3. Reset priority Remarks 1. = bus clock (33 MHz to 16.7 MHz) 2. m = intermediate clock 148 CHAPTER 10 TIMER/COUNTER FUNCTION (2) Timer 4 (16-bit interval timer) Figure 10-2. Block Configuration of Timer 4 /2 /8 m m/16 m/32 Note TM4 (16 bits) Clear & start CM4 INTCM4 Note Internal count clock Remarks 1. = bus clock (33 MHz to 16.7 MHz) 2. m = intermediate clock 10.2.1 Timer 1 (1) Timer 1 (TM1) Timer 1 functions as a 16-bit timer/event counter. It is mainly used to measure cycles and frequencies. It can be also used to output pulses. The TM1 register can be only read in 16-bit units. Figure 10-3. Timer 1 (TM1) Address: C0000078H 15 TM1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R The timer can be started or stopped by the timer control 1 (TMC1) (refer to Figure 10-8. Timer Control Register 1 (TMC1)). The internal/external count clock can be selected by using the TMC1 register. (a) External count clock The TM1 operates as an event counter when an external count clock is selected. The valid edge of the count clock is specified by the timer unit mode register (TUM1) and the value of TM1 is counted up by the TI pin input. 149 CHAPTER 10 TIMER/COUNTER FUNCTION (b) Internal count clock When the internal count clock is selected, TM1 operates as a free running timer. TM1 is counted up by the internal clock (/2 to /64) specified by the TMC1 register. When the internal clock is selected, m (intermediate clock) is selected from /2 or /4 by the prescaler at the preceding stage, and then the final count clock is selected from m, m/4, or m/16 by the prescaler at the following stage. This means that a total of six different count clocks can be selected. When the timer overflows, an overflow interrupt (INTOV1) can be generated. The timer can be stopped after it has overflown, by using the TUM1 register. The TUM1 register can also be used to clear and start the timer by an external input signal (TCLR). At this time, the prescaler is also cleared. Therefore, the time from input of the external signal (TCLR) to the first timer count up is fixed depending on the division ratio of the prescaler. Caution The count clock cannot be changed during timer operation. (c) Setting of capture/compare register * As capture register An interrupt signal (INTCC10 through INTCC13) is generated by an external input signal (INTP10 through INTP13). The valid edges of INTP10 through INTP13 can be selected from the rising edge, falling edge, or both the rising and falling edges by using the external interrupt mode register (IMOD) (refer to Figure 4-10. ICU Mode Register (IMOD)). * As compare register An interrupt signal (INTCC10 through INTCC13) can be generated in response to the coincidence signal from the compare register if so set by the TUM1 register (refer to Figure10-7. Timer Unit Mode Register (TUM1)). Caution Do not change the mode during timer operation. 150 CHAPTER 10 TIMER/COUNTER FUNCTION 10.2.2 Timer 4 (1) Timer 4 (TM4) Timer 4 functions as a 16-bit timer. It is mainly used as an interval timer for software. The TM4 register can be only read in 16-bit units. Figure 10-4. Timer 4 (TM4) Address: C000008AH 15 TM4 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R The timer can be started or stopped by the timer control register (TMC4). The following count clock can be selected by using the TMC4 register. First, m (intermediate clock) is selected from /2 or /8 by the prescaler at the preceding stage, and then the count clock is selected from m/16 or m/32 by the prescaler at the following stage. This means a total of four types of count clocks can be selected. The TM4 is cleared to 0 by the coincidence signal issued from the compare register, and counting up is resumed. Cautions 1. When the TM4 is used as an interval timer, because the timer is cleared by the next count clock if the value of the compare register coincides with the timer register value, the value of the timer may not be 0 even if it has been read immediately after the coincidence interrupt has occurred if the division ratio is too high. 2. The count clock cannot be changed during timer operation. (2) Compare register (CM4) CM4 is a 16-bit register and is connected to TM4. It can be read or written in 16-bit units. Figure 10-5. Compare Register (CM4) Address: C000008CH 15 CM4 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W 151 CHAPTER 10 TIMER/COUNTER FUNCTION 10.2.3 Capture/compare registers (CC10 through CC13) The capture/compare registers (CC10 through CC13) can be used as capture registers or compare registers depending on the specification by the TUM1 register. These registers can be read or written in 16-bit units. Figure 10-6. Capture/Compare Registers (CC10 through CC13) Address of CC10: C0000080H Address of CC11: C0000082H Address of CC12: C0000084H Address of CC13: C0000086H 15 CC10-CC13 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W: - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W - R/W A compare register is used to compare its value with the count value of the timer at each count clock of the timer connected. When the value of the compare register coincides with the count value of the timer, a coincidence signal is issued. The coincidence signal of the compare register is used to generate an interrupt request. Each compare register has a set/reset output function. The corresponding timer output is set or reset by this function in synchronization with generation of the coincidence signal. A capture register latches the value of the timer connected (asynchronous with the count clock) when it detects the valid edge of the corresponding interrupt request signal input pin (INTP10 through INTP13), using this signal as a capture trigger. (1) As capture register When a capture/compare register is used as a capture register, an interrupt is generated when the valid edge of the input pin (INTP1n) is detected. At this time, an interrupt cannot be generated by the coincidence signal INTCC1n of the compare register (n = 0 to 3). If the capture (latch) timing of the capture register and a write operation to the register by an instruction contend, the latter takes precedence, and the capture operation is ignored. (2) As compare register When a capture/compare register is used as a compare register, coincidence signal INTCC1n or the valid edge of the input pin (INTP1n) can be selected as an interrupt signal by using the TUM1 register. When INTP1n is selected, an external interrupt can be accepted in parallel with the specification of the timer output (n = 0 to 3). The compare register compares its value with the count value of TM1. A value must be assigned to the CC1n register specified as a compare register. Even when all the four registers CC10 through CC13 are specified as compare registers, for example, and the compare results of only two of them are used, assign an arbitrary value to the remaining two registers. Otherwise, the operation is not guaranteed. The following table lists the functions of the capture/compare registers and compare registers. 152 CHAPTER 10 TIMER/COUNTER FUNCTION Table 10-1. Capture/Compare Registers Generated Interrupt Signal INTCC10 INTCC11 INTCC12 INTCC13 INTOV1 INTCM4 Timer Output (Set/Reset) TO10 (Set) TO10 (Reset) TO11 (Set) TO11 (Reset) - - - - Timer TM1 Register CC10 CC11 CC12 CC13 TM1 Timer Restart - - - - - { Capture Trigger INTP10 INTP11 INTP12 INTP13 Other Function - - - - External clear - TM4 CM4 153 CHAPTER 10 TIMER/COUNTER FUNCTION 10.3 Timer/Counter Control Registers 10.3.1 Timer unit mode register (TUM1) The TUM1 register specifies the operation modes of the capture/compare registers. This register can be read or written in 16-bit units. Figure 10-7. Timer Unit Mode Register (TUM1) (1/2) Address: C0000072H 15 TUM1 0 14 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OST ECLR1 TES11 TES10 CES11 CES10 CMS13 CMS12 CMS11 CMS10 IMS13 IMS12 IMS11 IMS10 Initial value: R/W: 0 R 0 R 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 13 Bit Name OST Overflow Stop Description Specifies an operation after the timer has overflowed. This flag is valid only for TM1. 0: Timer continues counting up after overflow. 1: Timer holds 0000H and stops after overflow. At this time, the CE1 bit of the TMC1 register remains 1. The timer resumes counting up by the following operation. * Writing 1 to the CE1 bit (When ECLR1 = 0) * Trigger input to the timer clear pin (TCLR1) (When ECLR1 = 1) 12 ECLR1 External Input Timer Clear Enables clearing the timer by inputting an external clear signal (TCLR) to TM1. 0: Does not clear TM1 by external input. 1: Clears TM1 by external input. After cleared, TM1 starts counting up. 11, 10 TES11, TES10 TI1 Edge Select Specifies the valid edge of the external clock input (TI1). TES11 0 0 1 1 9, 8 CES11, CES10 TES10 0 1 0 1 Valid edge RFU (reserved) RFU (reserved) Rising edge (initial value) Both rising and falling edges TCLR1 Edge Select Specifies the valid edge of the external clear input (TCLR). CES11 0 0 1 1 CES10 0 1 0 1 Valid edge RFU (reserved) RFU (reserved) Rising edge (initial value) Both rising and falling edges 154 CHAPTER 10 TIMER/COUNTER FUNCTION Figure 10-7. Timer Unit Mode Register (TUM1) (2/2) Address: C0000072H 15 TUM1 0 14 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OST ECLR1 TES11 TES10 CES11 CES10 CMS13 CMS12 CMS11 CMS10 IMS13 IMS12 IMS11 IMS10 Initial value: R/W: 0 R 0 R 0 R/W 0 R/W 1 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Bit 7-4 Bit Name CMS13 - CMS10 Capture/Compare Mode Select Description Select the operation modes of the capture/compare registers (CC13 through CC10). 0: Operate as capture registers. However, the capture operation is performed only when the CE bit of the TMC1 register is 1. 1: Operate as compare registers. 3-0 IMS13 - IMS10 Interrupt Mode Select Selects INTP1n or INTCC1n as an interrupt source (n = 3 to 0). 0: Uses coincidence signal (INTCC1n) of compare register as interrupt request signal. 1: Uses an external input signal (INTP1n) as an interrupt request signal. Caution If the CMS1n and IMS1n are changed during the timer operation, these operations are not guaranteed (n = 3 to 0). 155 CHAPTER 10 TIMER/COUNTER FUNCTION 10.3.2 Timer control register 1 (TMC1) TMC1 controls the operation of timer 1 (TM1) and can be read or written in 8-bit units. Figure 10-8. Timer Control Register 1 (TMC1) Address: C0000074H 7 TMC1 CE1 6 0 5 0 4 3 2 1 0 0 ETI PRS11 PRS10 PRM11 Initial value: R/W: 0 R/W 0 R 0 R 0 R/W 0 R/W 0 R/W 0 R/W 0 R Bit 7 Bit Name CE1 Count Enable Controls the timer operation. Description 0: Timer is cleared to 0000H and does not operate. 1: Timer performs count operation. If ECLR1 bit of TUM1 = 1, however, the timer does not count up until the timer clear signal (TCLR) is input. When the ECLR1 bit of TUM1 is 1, setting the CE1 bit to 1 starts counting of the timer. Therefore, even if the ECLR1 bit is cleared to 0 after the CE1 bit has been set with ECLR1 bit = 1, the timer does not start. 4 ETI External TI1 Input Specifies an external or internal count clock. 0: Specifies (internal) 1: Specifies TI1 (external) 3, 2 PRS11, PRS10 Prescaler Clock Select Selects an internal count clock ( m: intermediate clock). PRS11 0 0 1 1 PRS10 0 1 0 1 Count clock m m/4 RFU (reserved) m/16 1 PRM11 Prescaler Clock Mode Specifies intermediate clock m of the count clock (: bus clock). 0: /2 1: /4 Caution If the clock is changed during the count operation, the operation is not guaranteed. To change the clock, stop the count operation. 156 CHAPTER 10 TIMER/COUNTER FUNCTION 10.3.3 Timer control register 4 (TMC4) TMC4 controls the operation of timer 4 (TM4) and can be read or written in 8-bit units. Figure 10-9. Timer Control Register 4 (TMC4) Address: C0000088H 7 TMC4 CE4 6 0 5 0 4 0 3 0 2 1 0 PRS40 PRM41 PRM40 Initial value: R/W: 0 R/W 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 7 Bit Name CE4 Count Enable Controls the operation of the timer. Description 0: Timer is cleared to 0000H and stops. 1: Timer performs count operation. 2 PRS40 Prescaler Clock Select Selects an internal count clock ( m: intermediate clock). 0: m/16 1: m/32 1, 0 PRM41, PRM40 Prescaler Clock Mode Specifies intermediate clock m of the count clock (: bus clock). PRM41 0 0 1 1 PRM40 0 1 0 1 m /2 RFU (reserved) /8 RFU (reserved) Caution If the clock is changed during the count operation, the operation is not guaranteed. To change the clock, stop the count operation. 157 CHAPTER 10 TIMER/COUNTER FUNCTION 10.3.4 Timer output control register (TOC1) TOC1 specifies timer output modes and can be read or written in 8-bit units. Figure 10-10. Timer Output Control Register (TOC1) Address: C0000076H 7 TOC1 6 5 4 3 0 2 0 1 0 ETNO11 ALV11 ETNO10 ALV10 TOPC11 TOPC10 Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 1 R/W 1 R/W Bit 7, 5 Bit Name ENTO11, ENTO10 Enable TOxx pin Description Enables the corresponding timer output (TO11 or TO10). 0: The timer output is disabled. The corresponding TO11 or TO10 pin outputs a level in reverse phase to the ALV bit (inactive level). Even if a coincidence signal is generated from the corresponding compare register, the level of the TO11 or TO10 pin does not change. 1: The timer output is enabled. The timer output changes if a coincidence signal is generated from the corresponding compare register. A level in reverse phase to the ALV bit (inactive level) is output until the coincidence signal is generated first since the timer output has been enabled. 6, 4 ALV11, ALV10 Active Level TOxx pin Specifies the active level of the timer output. 0: Active level is low (0). 1: Active level is high (1). 1 TOPC11 Prescaler Clock Mode Selects the function of the multiplexed pin TO11/INTP12. 0: TO11 output 1: INTP12 input (initial value) 0 TOPC10 Prescaler Clock Mode Selects the function of the multiplexed pin TO10/INTP10. 0: TO10 output 1: INTP10 input (initial value) Caution The TO10 and TO11 output does not change with the external interrupt signal (INTP1n). When using TO10 and TO11, specify the capture/compare registers as compare registers (CMS1n = 1) (n = 0 to 3). Remark Flip-flop of TO10 and TO11 outputs gives priority to reset. 158 CHAPTER 10 TIMER/COUNTER FUNCTION 10.3.5 ICU mode register (IMOD) This control register specifies the valid edge of an external interrupt signal. When CC1n of TM1 is used as a capture register, this register detects the valid edge of an external interrupt (INTP1n) as a capture trigger (n = 0 to 3). This valid edge can be specified by the ICU mode register (IMOD) (for details, refer to 4.6.5 ICU mode register (IMOD)). 10.3.6 Timer overflow status register (TOVS) This register stores overflow flags from timers 1 and 4 (TM1 and TM4). It can be read or written in 8-bit units. Occurrence of an overflow can be polled by testing and resetting this TOVS register by software. Figure 10-11. Timer Overflow Status Register (TOVS) Address: C0000070H 7 TOVS 0 6 0 5 0 4 OVF4 3 0 2 0 1 OVF1 0 0 Initial value: R/W: 0 R 0 R 0 R 0 R/W 0 R 0 R 0 R/W 0 R Bit 4, 1 Bit Name OVF4, OVF1 Overflow Flag TMn (n = 4 or 1) overflow flag 0: TMn does not overflow. 1: TMn overflows. Description Because the TOVS register is of master/slave configuration, data cannot be transferred to the slave (to the TOVS register) during an access period by the CPU. Therefore, even if an overflow occurs while the TOVS register is read, the value of the flag is not affected, but is reflected on the second reading. Caution TM1 generates an interrupt request signal (INTOV1) to the interrupt controller in synchronization with the overflow. However, the interrupt operation and TOVS are completely independent, and INTOV1 does not occur even if 1 is written to OVF1. The flag can be cleared by writing 0 to OVF1. 159 CHAPTER 10 TIMER/COUNTER FUNCTION 10.4 Operation 10.4.1 Timer 1 Timer 1 functions as a 16-bit free running timer or an event counter of external signals. The operation of this timer 1 specified by the timer control register 1 (TMC1). Timer 1 counts up the internal clock (/2 to /64) specified by the PRS11, PRS10, and PRM11 bits of the TMC1 register, or external clock input (TI). If the external clock is specified as the count clock at this time, TM1 operates as an event counter. If the timer overflows as a result of counting, an overflow interrupt (INTOV1) is generated. If the count value of TM1 coincides with the value of the CC10 through CC13 registers when TM1 operates as a free running timer, interrupt signals (INTCC10 through INTCC13) are generated and the timer output signals (TO10 and TO11) can be set or reset. The count value of TM1 can be captured to the CC10 through CC13 registers (capture operation) in synchronization with the valid edge detected from external interrupt request input pins (INTP10 through INTP13) as external triggers. The captured value is retained until the next capture trigger is generated. Figure 10-12. Basic Operation of Timer 1 Count clock TM1 0000H 0001H 0002H 0003H Count starts CE1 1 FBFEH FBFFH 0000H 0001H 0002H 0003H Count starts CE1 1 Count disabled CE1 0 If both the rising and falling edges are specified as the capture triggers, the width of a pulse input from an external source can be measured. If the rising edge is specified as the capture trigger, the cycle of the input pulse can be measured. 160 CHAPTER 10 TIMER/COUNTER FUNCTION Figure 10-13. Example of Capture Operation FFFFH Count value (TM1) D1 D0 0 D2 Count starts CE1 1 Interrupt request (INTP10) Capture register (CC10) D0 D1 D2 10.4.2 Timer 4 Timer 4 functions as a 16-bit interval timer. The operation of this timer is specified by the timer control register 4 (TMC4). Timer 4 counts up the internal clock (/32 to /256) specified by the PRS40, PRM41, and PRM40 bits of the TMC4 register. If the value of TM4 coincides with the value of CM4 as a result of counting, TM4 is cleared, and at the same time, a coincidence interrupt (INTCM4) occurs. This coincidence interrupt (INTCM4) can be used to execute DMA transfer (refer to CHAPTER 8 DMA FUNCTION). Figure 10-14. Basic Operation of Timer 4 Count clock TM4 0000H 0001H 0002H 0003H Count starts CE4 1 FBFEH FBFFH 0000H 0001H 0002H 0003H Count starts CE4 1 Count disabled CE4 0 161 CHAPTER 10 TIMER/COUNTER FUNCTION If coincidence is detected as a result of a compare operation, TM4 is cleared to 0 by the next count clock input. This function allows TM4 to operate as an interval timer at a count clock cycle of the value set to CM4 plus 1. Figure 10-15. Example of Compare Operation n n Count value (TM4) 0 Clear Clear Count starts CE4 1 Interrupt request (INTCM4) t Remark n : Value of CM4 register t : Interval cycle = (n+1) x Count clock cycle 10.5 Notes Coincidence is always detected by the compare register immediately after the timer has counted up. Coincidence does not take place in the following cases. (1) When compare register is rewritten (TM1, TM4) Count clock Timer value n-1 n n+1 Compare register value m n Coincidence detection L Write to register Coincidence does not occur Coincidence does not occur 162 CHAPTER 10 TIMER/COUNTER FUNCTION (2) When TM1 is cleared by external signal Count clock Timer value n-1 n 0 1 External clear input Compare register value 0000H Coincidence detection L Coincidence does not occur (3) When TM4 is cleared (when compare register value = 0000H) Count clock Timer value 65534 65535 0 0 1 Internal coincidence clear Coincidence detection Coincidence does not occur Caution The value of timer is cleared to 0 when the timer overflows if the timer operates as a free running timer. Count clock Timer value 65534 65535 0 1 2 Overflow interrupt 163 [MEMO] 164 CHAPTER 11 PORT FUNCTION The ports of the V831 are 3-bit I/O ports that can be set in the input or output mode in 1-bit units. In addition to the port function, these ports are also used as the I/O lines of the clocked serial interface (CSI) in the control mode. Table 11-1. Operation in Control Mode Port Port 0 Port 1 Port 2 Control Mode SCLK SO SI Remark Multiplexed with I/O line of clocked serial interface (CSI) 11.1 Configuration (1) Configuration of port 0 Figure 11-1. Block Diagram of Port 0 Control mode register (PC) Internal peripheral I/O bus Mode register (PM) Selector SCLK output Port register (PORT) PORT0 Selector SCLK input 165 CHAPTER 11 PORT FUNCTION (2) Configuration of port 1 Figure 11-2. Block Diagram of Port 1 Control mode register (PC) Internal peripheral I/O bus Mode register (PM) Selector SO Port register (PORT) PORT1 (3) Configuration of port 2 Figure 11-3. Block Diagram of Port 2 Control mode register (PC) Internal peripheral I/O bus Mode register (PM) Port register (PORT) Selector Selector PORT2 SI 166 CHAPTER 11 PORT FUNCTION 11.2 Port Control Register 11.2.1 I/O port register (PORT) This register is for the 3-bit I/O port, PORT, and can be read or written in 8-bit units. In the input mode, the levels of the port pins can be directly read from this register. However, the register does not retain the values. In the output mode, the values written to this register are output to the port pins. Figure 11-4. I/O Port Register (PORT) Address: C0000000H 7 PORT 0 6 0 5 0 4 0 3 0 2 1 0 PORT2 PORT1 PORT0 Initial value: R/W: - R - R - R - R - R - R/W - R/W - R/W 11.2.2 I/O mode register (PM) This register sets PORT in the input mode or output mode in 1-bit units, and can be read or written in 8-bit units. Figure 11-5. I/O Mode Register (PM) Address: C0000002H 7 PM 1 6 1 5 1 4 1 3 1 2 1 0 PM2 PM1 PM0 Initial value: R/W: 1 R 1 R 1 R 1 R 1 R 1 R/W 1 R/W 1 R/W Bit 2-0 Bit Name PM2 - PM0 Port Mode Description Specifies the input/output mode of PORT0 through 2 pins. 0: Output mode (output buffer ON) 1: Input mode (output buffer OFF) 167 CHAPTER 11 PORT FUNCTION 11.2.3 Port control mode register (PC) This register sets the control modes to select the pot or CSI operation and can be read or written in 8-bit units. Figure 11-6. Port Control Mode Register (PC) Address: C0000004H 7 PC 0 6 0 5 0 4 0 3 0 2 PC2 1 PC1 0 PC0 Initial value: R/W: 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W Bit 2-0 Bit Name PC2 - PC0 Port Control Description Specifies the operation mode of PORT2 through PORT0 pins PC2 0 1 Others PC1 0 1 PC0 0 1 Operation mode I/O port mode CSI interface Reserved (setting prohibited) Caution Set the CLS02 through CSL00 bits of the clocked serial interface mode register (CSIM0) of CSI (refer to 9.2) before setting the port control mode register (PC). 168 CHAPTER 12 CLOCK GENERATION FUNCTION The clock generator generates and controls the CPU clock and bus clock () supplied to the internal hardware units, including the CPU. Table 12-1. Multiplication Function by PLL Synthesizer Specification Bus clock () CPU clock 16.7 - 33 MHz (fB) 50 - 100 MHz (3 x fB) Remark PLL: Phase Locked Loop 12.1 Configuration Figure 12-1. Block Diagram of Clock Generation Function PLL synthesizer 1/6 X1 OSC X2 fB Phase comparator 200 MHz 1/2 PDF VCO 33 MHz Bus clock CPU clock 100 MHz fB : Oscillation frequency or external clock frequency : Bus clock OSC: Oscillator PFD: Phase Frequency Detector VCO: Voltage Controlled Oscillator 169 CHAPTER 12 CLOCK GENERATION FUNCTION 12.2 Selecting Input Clock The clock generator consists of a clock oscillator and a PLL synthesizer. For example, a bus clock of 33 MHz and a CPU clock of 100 MHz can be generated by connecting a 33 MHz crystal resonator or ceramic resonator between the X1 and X2 pins. An external clock can be directly connected to the oscillator. In this case, input the clock signal to the X2 pin, and open the X1 pin. 12.2.1 Lockup time Immediately after the power has been applied or the STOP mode has been released, the PLL is in the phase lock status at a specific frequency, and it takes a certain time (lockup time) until the frequency of the PLL is stabilized. The status until the stabilization is called unlock status, and the stabilization status is called lock status. Immediately after power application or releasing the STOP mode by the RESET signal, make sure that this stabilization time elapse, by using the RESET signal (refer to 13.4 Ensuring Oscillation Stabilization Time). When the STOP mode is released by the NMI signal, the oscillation stabilization time is automatically ensured. 12.3 Clock Output Control The operations of the CLKOUT pin can be selected by the COE bit of the clock control register (CGC). The power consumption can be effectively reduced by using the standby mode (HALT or STOP) (power management mode). 12.3.1 Clock output disable mode In this mode, output of the clock from the CLKOUT pin is disabled. pin can be suppressed. Figure 12-2. Clock Output Disable Mode CLKOUT (normal mode) CLKOUT (clock output disable mode) Because the operation of CLKOUT is completely stopped, the power consumption can be substantially reduced and the noise radiation from the CLKOUT Fixed to "L" 170 CHAPTER 12 CLOCK GENERATION FUNCTION 12.4 Clock Control Registers 12.4.1 Clock control register (CGC) This register controls output of CLKOUT. It can be read or written in 8-bit units. Figure 12-3. Clock Control Register (CGC) Address: C00000E0H 7 CGC 6 KEY 5 4 3 CESEL 2 0 1 0 0 COE Initial value: R/W: 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 1 R/W Bit 7-4 Bit Name KEY KEY Data Description Identifies data. Be sure to set these bits to "0111". No data can be written to the CESEL and COE bits if the value of the KEY data is not "0111". These bits are always "0000" when read. 3 CESEL Crystal External Select Specifies the functions of the X1 and X2 pins. 0: Connect a resonator to the X1 and X2 pins. 1: Connect an external clock to the X2 pin and leave the X1 pin unconnected. 0 COE Clock Out Enable Enables or disables output of CLKOUT. 0: Disables output (CLKOUT pin is fixed to low level). 1: Enables output. 171 CHAPTER 12 CLOCK GENERATION FUNCTION 12.4.2 PLL control register (PLLCR) This register indicates the status of the PLL. This register is mapped to the I/O space and can be only read in 32bit units. Figure 12-4. PLL Control Register (PLLCR) Address: FFFFFFF8H 31 PLLCR Reserved 43 CM 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 R/W: R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Bit 31 - 4 3-0 Bit Name Reserved CM Reserved field Clock Mode Description These bits are always "0010" when read. CM 0 0 0 0 0 1 0 0 0 0 1 x 0 0 1 1 x x 0 1 0 1 x x CPU clock: bus clock Reserved Reserved 3:1 Reserved Reserved Reserved 172 CHAPTER 13 STANDBY FUNCTION The V831 has a standby function to control the operating clock and reduce the power consumption. This function can be used in the following two modes: * * HALT mode (stops only the CPU clock) STOP mode (stops the entire system, including the clock generator) Each of these modes can be set by executing the HALT or STBY instruction. 13.1 Standby Mode The following two standby modes can be used. (1) HALT mode In this mode, the clock generator (oscillator and PLL synthesizer) operates, but the operating clock of the CPU is stopped. The other internal peripheral functions are supplied with the clock and continue operation. By using this mode in combination with the normal mode, the power consumption of the entire system can be reduced. (2) STOP mode In this mode, the clock generator (PLL synthesizer) is stopped and the entire system is stopped. Because the PLL synthesizer and internal peripheral functions are stopped, the power consumption can be reduced more than in the HALT mode. Because the clock output of the PLL synthesizer is stopped, make sure that sufficient time elapses after the STOP mode is released until the oscillator, CPU clock, and bus clock are stabilized. The PLL circuit may require lock up time depending on the program. Table 13-1 shows the operations of the clock generator in the HALT and STOP modes. By selecting each mode as the application requires, the power consumption of the system can be efficiently reduced. Table 13-1. Operation of Clock Generator in Standby Mode Clock Supply to Peripheral I/O { { x Clock Supply to CPU { x x Standby Mode Normal mode HALT mode STOP mode Oscillator (OSC) { { { PLL Synthesizer { { x Remark { : Operates x : Stopped 173 CHAPTER 13 STANDBY FUNCTION Figure 13-1. Status Transition Normal Released by RESET or NMI input Released by RESET, NMI, or maskable interrupt input HALT instruction execution STBY instruction execution STOP mode HALT mode 13.2 HALT mode 13.2.1 Setting and operating status of HALT mode In the HALT mode, the clock generator (oscillator and PLL synthesizer) operates, but the operating clock of the CPU is stopped. The other internal peripheral functions are supplied with the clock and continue operation. When the HALT instruction is executed, the HALT mode is set. If the HALT mode is set while the CPU is not operating, the overall power consumption of the system can be reduced. In the HALT mode, program execution is stopped, but the previous contents of all the registers are retained. HALT mode is accepted. To set the HALT mode in the non-maskable interrupt service routine, enable acknowledgment of a new nonmaskable interrupt request by clearing PSW.NP to 0 (status in which NMI is not serviced) before executing the HALT instruction. If PSW.NP is not 0, the normal operation mode cannot be restored from the HALT mode by NMI. Table 13-2 shows the hardware status in the HALT mode. In addition, the on-chip peripheral functions independent of the instruction processing of the CPU continue operation. The HLDRQ signal in the 174 CHAPTER 13 STANDBY FUNCTION Table 13-2. Operating Status in HALT Mode Function Oscillator PLL synthesizer Bus clock CPU Port output Peripheral function Internal data Operates Operates Operates Stops Retained Operates Internal data such as registers of CPU retain status before HALT mode is set. Undefined High impedance when HLDAK = 0 Operating Status Note 1 A1 - A23 D0 - D31 BCYST CS1 - CS7 IORD, IOWR MRD, WE, OE, LLMWR, LUMWR, ULMWR, UUMWR REFRQ, LLCAS, LUCAS, ULCAS, UUCAS RAS HLDRQ CLKOUT High impedance 1 High impedance when HLDAK = 0 1 Note 2 Note 3 Operates Clock output (when clock output is not disabled) Notes 1. Each pin is in the operating status during DMA transfer. 2. Other than CBR refresh 3. The previous status is retained before CBR refresh is executed. This pin is set to "1" after CBR refresh. 13.2.2 Releasing HALT mode The HALT mode can be released by the non-maskable interrupt request, an unmasked maskable interrupt request, and RESET pin input. (1) Releasing by non-maskable interrupt request When the NMI signal is detected, supply of the CPU clock is resumed. (2) Releasing by maskable interrupt request Supply of the CPU clock is resumed by an unmasked maskable interrupt request. To set the HALT mode in an interrupt routine, enable the interrupt that releases the HALT mode before executing the HALT instruction. Enable the interrupt (PSW.ID = 0, EP = 0) and set the interrupt enable level. 175 CHAPTER 13 STANDBY FUNCTION Table 13-3. Releasing HALT Mode by Interrupt Request Releasing Source Non-maskable interrupt request Maskable interrupt request EI Status (PWS.ID = 0) Handler address branch Handler address branch Not released DI Status (PSW.ID = 1) (3) Releasing by RESET pin input Same as the normal reset operation. Therefore, the status of the register before the standby mode is set is not retained. 13.3 STOP Mode 13.3.1 Setting and operating status of STOP mode In the STOP mode, the PLL synthesizer is stopped (the oscillator is not stopped). The power consumption can be reduced by stopping the PLL synthesizer and internal peripheral circuit. When the STBY instruction is executed, the CBR self refresh cycle is started, and the STOP mode is set. Make sure that the oscillation stabilization time elapses after the STOP mode has been released. In the STOP mode, program execution is stopped, but the previous contents of all the registers are retained. In addition, the internal peripheral functions are also stopped. Because the internal peripheral functions and clock supply by CLKOUT are stopped in the STOP mode, confirm that the internal peripheral functions and external peripheral functions have stopped before setting the STOP mode, and then execute the STBY instruction. Before executing the STBY instruction, disable DMA transfer by clearing the EN bit of DCHC0 through DCHC3 of DMAC to 0. To set the STOP mode in the non-maskable interrupt service routine, enable acknowledgment of a new nonmaskable interrupt request by clearing PSW.NP to 0 (status in which NMI is not serviced) before executing the STBY instruction. If PSW.NP is not 0, the normal operation mode cannot be restored from the STOP mode by NMI. Table 13-4 shows the hardware status in the STOP mode. 176 CHAPTER 13 STANDBY FUNCTION Table 13-4. Operating Status in STOP Mode Function Oscillator PLL synthesizer Bus clock CPU Port output Peripheral function Internal data Operates Stops Stops Stops Retained Stops Internal data such as registers of CPU retain status before STOP mode is set. Undefined High impedance 1 Operating Status A1 - A23 D0 - D31 BCYST CS1 - CS7 IORD, IOWR MRD, WE, OE, LLMWR, LUMWR, ULMWR, UUMWR REFRQ, RAS, LLCAS, LUCAS, ULCAS, UUCAS HLDRQ CLKOUT CBR self refresh Note Not accepted 0 Note CBR self refresh is not executed when it is disabled. In this case, the status of this pin before the STOP mode is set is retained. 13.3.2 Releasing STOP mode The STOP mode is released by the non-maskable interrupt request or RESET pin input. Make sure that the oscillation stabilization time of the oscillator elapses after the STOP mode has been released. 177 CHAPTER 13 STANDBY FUNCTION (1) Releasing by non-maskable interrupt request (NMI) When the NMI signal is detected, the PLL synthesizer resumes operation. After that, it starts supplying the CPU clock and bus clock after the oscillation stabilization time has elapsed. The interrupt processing started by the NMI signal when the STOP mode is released is treated as equivalent to the normal non-maskable interrupt processing. If the two must be distinguished in a program, prepare a software status in advance, and set the status before executing the STBY instruction. When this status is checked by the non-maskable interrupt processing, the NMI signal releasing the STOP mode can be distinguished from the normal NMI signal. (2) Releasing by RESET input Same as the normal reset operation. Therefore, the values of the registers before the standby mode is set are not retained. 13.4 Ensuring Oscillation Stabilization Time After the STOP mode has been released, enough time must elapse until the PLL circuit operation stabilizes. (1) To ensure lapse of time by using oscillation stabilization time ensuring timer (NMI signal input) The STOP mode is released if a valid edge is input to the NMI pin. In this case, the oscillation stabilization time required for clock output to be stabilized is ensured by the oscillation stabilization time ensuring timer. After a specific time, clock output is started, and execution branches to the handler address of the NMI processing. 178 CHAPTER 13 STANDBY FUNCTION Figure 13-2. STOP Mode Releasing Timing (with NMI signal input) CLKOUT (output) STOP status NMI (input) PLL circuit stops PLL circuit stabilization time PLL circuit stabilization time: 31 ms (resonator or external clock: 33 MHz) 62.8 ms (resonator or external clock: 16.7 MHz) (2) To ensure time lapse by signal level width (RESET signal input) When a falling edge is input to the RESET pin, the STOP mode is released. Ensure that the time during which clock output from the oscillator is stabilized elapses by using the low-level width input to the RESET pin. Input the low-level width for 20 ms or longer to stabilize the PLL. After a rising edge is input to the RESET pin, supply of the clock is started, and execution branches to the handler address that is used for system reset. Figure 13-3. STOP Mode Releasing Timing (with RESET signal input) CLKOUT (output) STOP status RESET (input) PLL circuit stabilization time (20 ms or longer) Internal system reset signal PLL circuit stops 179 [MEMO] 180 CHAPTER 14 RESET/NMI CONTROL FUNCTION The reset/NMI control functions are implemented by the system control unit (SYU). The system control unit is a circuit that controls the RESET and NMI signals. 14.1 Features * * RESET and NMI pins have noise rejection circuit using the external input clock sampling. Performs forced reset, reset mask, and NMI mask processing from debug control unit 14.2 Non-Maskable Interrupt (NMI) The NMI signal is sampled at the rising edge of the external input clock (this clock is not stopped even in the STOP mode and its cycle is the same as that of the bus clock). Noise of less than 5 external input clocks is rejected and then the valid edge of the NMI signal is detected. Therefore, the NMI signal must be kept low for the duration of 5 external input clocks or longer. When the NMI signal goes low, the interrupt is detected. Because the NMI signal is detected at the falling edge, it can be deasserted inactive once the non-maskable interrupt request has been detected. The detected interrupt request is retained in the CPU until the CPU starts the interrupt processing. 14.3 Reset The system is reset and the on-chip hardware units are initialized when a low level is input to the RESET pin. When the RESET pin goes high, the reset status is cleared, and the CPU starts program execution. Initialize the contents of each register in software as necessary. The valid edge of the RESET signal is detected after noise width of less than 5 external input clocks has been rejected. Therefore, the RESET signal must be kept low for the duration of 5 external input clocks or longer. To satisfy the minimum width (20 clocks) of the reset enable for the CPU core, the width of the external reset signal must be 25 external input clocks or wider. The minimum number of clocks required for the first BCYST signal to be asserted active after the reset signal has been cleared is 10 bus clocks. 14.3.1 Pin function Table 14-1 shows the status of the output pins during the system reset period and immediately after reset. This status is retained during the reset period. If the HLDRQ signal is inactive after the RESET pin is kept low for the duration of 25 external input clocks or longer and then it is deasserted inactive, a memory read cycle is started to fetch instructions. Keep the HLDRQ signal inactive during power-ON reset. Connect a pull-up or pull-down resistor to the pins that go into a high-impedance state at reset. Otherwise, the memory contents may be lost when these pins go into a high-impedance state. 181 CHAPTER 14 RESET/NMI CONTROL FUNCTION The CLKOUT pin outputs the clock even during the reset period. Table 14-1. Status of Output Pin Immediately after Reset Function A1 - A23 D0 - D31 CS1 - CS7 BCYST IORD, IOWR WE, OE LLMWR, LUMWR, ULMWR, UUMWR LLCAS, LUCAS, ULCAS, UUCAS RAS CLKOUT HLDAK DMAAK0 - DMAAK3 PORT2/SI PORT1/SO PORT0/SCLK TXD DDO TRCDATA0 - TRCDATA3 TC/REFRQ TO10/INTP10, TO11/INTP12 Operating Status Undefined High impedance 1 1 1 1 1 1 1 Clock output 1 1 High impedance High impedance High impedance 1 Undefined Undefined 1 High impedance Figure 14-1. Accepting Reset Signal TWRLNote Oscillation clock RESET (input) Note The minimum value of TWRL (low-level period of the RESET signal) differs depending on the following status. * On power application or releasing STOP status (STBY instruction): 20 ms (stabilization time of oscillator + PLL oscillation stabilization time) * Normal (other than above): 25 clocks 182 CHAPTER 14 RESET/NMI CONTROL FUNCTION 14.3.2 Initialize Table 14-2 shows the value of each register after reset. Initialize the contents of each register in software as necessary. Care must be exercised in handling the clock control register (CGC) because this register is related to system setting (such as X1 and X2 pin functions and CLKOUT pin operation). Table 14-2. Initial Value of Each Register after Reset Register System registers Program counter Exception/interrupt status saving registers PC EIPC EIPSW NMI/dual exception status saving registers FEPC FEPS Exception cause register Program status word Processor ID register Task control word Debug exception status saving registers Note Initial Value after Reset FFFFFFF0H Undefined Undefined Undefined Undefined 0000FFF0H 00008000H 00008301H 000000E0H Undefined Undefined 00000000H 00000002H 00000000H xxxxx000H xxxxx000H Undefined ECR PSW PIR TKCW DPC DPSW Hardware configuration control register Internal registers PLL control register Note HCCW PLLCR CMCR ICTR DCTR IRAMR Cache memory control register Instruction cache tag register Data cache tag register Instruction RAM register Note These registers are fixed to the initial value with the V831. 183 [MEMO] 184 CHAPTER 15 DEBUG/TRACE FUNCTION The V831 has a debug control unit (DCU) that implements a debug/trace function. 15.1 Features * Signals for debug: 10 (dedicated: DRST, DCK, DMS, DDI, DDO, TRCDATA0 through TRCDATA3) (multiplexed: CLKOUT) * On-chip debugging can be executed if wiring and connectors for debugging are mounted on the user board (however, the fatal exception handler (FFFFFFE0H through FFFFFFEFH) cannot be used). Debug interface for interfacing the host machine via a debug unit is provided. Trace interface that monitors execution status of user program is provided. Forced reset function (can forcibly reset CPU core and peripheral functions) Forced break function (can forcibly stop user program execution) Can stop user program execution at any address. Can start user program execution from any address. User resources (such as memory and I/O) can be read or written while user program is stopped. User program can be downloaded. Mask function (can mask external input signals (RESET, HLDRQ, NMI, INTP00 through INTP03, and INTP10 through INTP13)) * * * Debug function * * * * * * * * Trace function * PC trace (branch trace) Can trace all branches (transition of processing) that take place during user program execution. Can select trace sources from the 9 classified branches by function. * Data trace Can trace all data accesses made via external data bus and internal peripheral I/O bus (internal data RAM, data cache, and system I/O of CPU core cannot be traced) Write data can be traced by write access. * * * Real-time trace Forced start/stop of trace. Starts trace from any execution PC. Trace buffer provided (PC trace and data trace multiplexed) Can store trace data of 8 to 40 sources 185 [MEMO] 186 APPENDIX A REGISTER INDEX [A] ASIM00 (asynchronous serial interface mode register 00)......................................................................................... 128 ASIM01 (asynchronous serial interface mode register 01)......................................................................................... 130 ASIS0 (asynchronous serial interface status register)................................................................................................ 131 [B] BCTC (bus cycle type control register)......................................................................................................................... 87 BPRM0 (baud rate generator prescaler mode register) ............................................................................................. 146 BRG0 (baud rate generator compare register) ........................................................................................................... 145 [C] CC10 through CC13 (capture/compare registers) ...................................................................................................... 152 CGC (clock control register) ....................................................................................................................................... 171 CM4 (compare register) ............................................................................................................................................. 151 CSIM0 (clocked serial interface register 0) ................................................................................................................ 138 [D] DBC (data bus width control register)........................................................................................................................... 88 DBC0 through DBC3 (DMA byte count registers 0 through 3) .................................................................................. 104 DC (DMA control register) .......................................................................................................................................... 109 DCHC0 through DCHC3 (DMA channel control registers 0 through 3) ...................................................................... 103 DDA0H through DDA3H (DMA destination address registers 0H through 3H) ......................................................... 103 DDA0L through DDA3L (DMA destination address registers 0L through 3L)............................................................. 104 DRC (DRAM configuration register) ............................................................................................................................. 94 DSA0H through DSA3H (DMA source address registers 0H through 3H) ................................................................. 101 DSA0L through DSA3L (DMA source address registers 0L through 3L).................................................................... 102 [I] ICR (interrupt clear register) ......................................................................................................................................... 46 IGP (interrupt group priority register)............................................................................................................................ 45 IMOD (ICU mode register) ................................................................................................................................... 48, 159 IMR (interrupt request mask register)........................................................................................................................... 47 IRR (interrupt request register)..................................................................................................................................... 47 [P] PC (port control mode register) .................................................................................................................................. 168 PIC (programmable idle control register)...................................................................................................................... 91 PLLCR (PLL control register) ..................................................................................................................................... 172 PM (I/O mode register) ............................................................................................................................................... 167 PORT (I/O port register) ............................................................................................................................................. 167 PRC (Page-ROM configuration register) ...................................................................................................................... 98 PWC0 (programmable wait control register 0).............................................................................................................. 89 PWC1 (programmable wait control register 1).............................................................................................................. 90 187 APPENDIX A REGISTER INDEX [R] RFC (refresh control register) ...................................................................................................................................... 96 RXB0, RXB0L (receive buffer) .................................................................................................................................... 132 [S] SIO0 (serial I/O shift register 0) ................................................................................................................................. 139 [T] TM1 (timer 1) .............................................................................................................................................................. 149 TM4 (timer 4) .............................................................................................................................................................. 151 TMC1 (timer control register 1) ................................................................................................................................... 156 TMC4 (timer control register 4) .................................................................................................................................. 157 TOC1 (timer output control register) ........................................................................................................................... 158 TOVS (timer overflow status register) ........................................................................................................................ 159 TUM1 (timer unit mode register) ................................................................................................................................ 154 TXS0, TXS0L (transmit shift register) ......................................................................................................................... 133 188 APPENDIX B GENERAL INDEX [A] A1 through A23 ............................................................30 Abort ..........................................................................122 Aborting by NMI signal ..............................................122 Address bus .................................................................30 Address multiplex function ...........................................94 Address space and block ............................................86 Asynchronous serial interface ...................................125 DC .............................................................................109 DCHC0 through DCHC3 ............................................103 DCK .............................................................................34 DDA0 through DDA3 .................................................103 DDI ..............................................................................34 DDO .............................................................................34 Debug control signal ....................................................34 Debug/trace function .................................................185 Demand transfer mode ..............................................111 DMA byte count registers 0 through 3 .......................104 DMA channel control registers 0 through 3 ................106 DMA control register ..........................................101, 109 DMA control signal ......................................................33 DMA destination address registers 0 through 3 ........103 DMA source address registers 0 through 3 ...............101 DMA transfer end interrupt ........................................119 DMA transfer end output ...........................................121 DMA transfer request .................................................113 DMA transfer type and subject to transfer .................111 DMAAK0 through DMAAK3 .........................................33 DMARQ0 through DMARQ3 ........................................33 DMS .............................................................................34 DRAM configuration register ........................................94 DRAM control function..................................................93 DRAM control signal.....................................................32 DRAM cycle..................................................................63 DRC..............................................................................94 DRST ...........................................................................34 DSA0 through DSA3 ..................................................101 [B] Baud rate generator ...................................................142 Baud rate generator compare register .......................145 Baud rate generator prescaler mode register ............146 BCTC ...........................................................................87 BCYST .........................................................................31 BPRM0 ......................................................................146 BRG0..........................................................................145 BT16B ..........................................................................31 Bus arbitration .............................................................83 Bus control signal ........................................................30 Bus cycle type control register ....................................87 Bus hold cycle .............................................................82 Bus sizing ....................................................................77 Bus sizing during DMA transfer .................................123 [C] Capture/compare register ..........................................152 CC10 through CC13 ..................................................152 CGC ...........................................................................171 CLKOUT ......................................................................31 Clock control register .................................................171 Clock output control ...................................................170 Clock output disable mode ........................................170 Clocked serial interface .............................................137 CPU core system register ............................................36 CS1 through CS7 ...................................................31, 32 CSI .............................................................................137 [E] Ensuring oscillation stabilization time.........................178 Exception processing ..................................................43 External I/O cycle ........................................................51 [G] GND..............................................................................28 GND_PLL ....................................................................28 [D] D0 through D31 ...........................................................30 Data bus ......................................................................30 Data bus width control register ....................................88 DBC .............................................................................88 DBC0 through DBC3 .................................................104 [H] HALT mode ...............................................................174 HLDAK..........................................................................30 HLDRQ .........................................................................30 189 APPENDIX B GENERAL INDEX [I] I/O mode register ....................................................... 167 I/O port register.......................................................... 167 ICR .............................................................................. 46 ICU mode register ............................................... 48, 159 Idle state ..................................................................... 77 IGP............................................................................... 45 IMOD .................................................................. 48, 159 IMR ............................................................................. 47 Initialize ..................................................................... 183 Internal block configuration ......................................... 23 Internal peripheral I/O space ....................................... 35 Internal unit ................................................................. 24 Interrupt clear register ................................................. 46 Interrupt control register .............................................. 45 Interrupt control signal ................................................. 32 Interrupt group priority register ................................... 45 Interrupt request mask register ................................... 47 Interrupt request register ............................................ 47 Interrupt requests by external input pins...................... 50 Interrupt/exception processing .................................... 37 INTP00 through INTP03 .............................................. 32 INTP10 through INTP13 ............................................. 32 IORD ........................................................................... 31 IOWR .......................................................................... 31 IRR .............................................................................. 47 [P] Page-ROM configuration register ............................... 98 Page-ROM control function ........................................ 98 Page-ROM cycle ......................................................... 60 PC.............................................................................. 168 PIC............................................................................... 91 Pin configuration (Top View)........................................ 21 PM ............................................................................. 167 PLL control register ................................................... 172 PLLCR ...................................................................... 167 PORT ........................................................................ 167 Port control mode register ......................................... 168 Port control register ................................................... 167 Port control signal ....................................................... 34 PORT0 through PORT2............................................... 34 PRC ............................................................................ 98 Priorities of DMA channel ......................................... 113 Priority of maskable interrupt ...................................... 42 Programmable idle control register.............................. 91 Programmable wait control register 0 ......................... 89 Programmable wait control register 1 ......................... 90 PWC0 ......................................................................... 89 PWC1 .......................................................................... 90 [R] RAS ............................................................................ 32 READY ....................................................................... 30 REFRQ ........................................................................ 32 Real-time pulse control signal ..................................... 33 Refresh function .......................................................... 96 Releasing HALT mode............................................... 175 Releasing STOP mode ............................................. 177 Request from DMARQ pin ......................................... 113 Request from internal peripheral hardware .............. 118 Request from software .............................................. 117 RESET ........................................................................ 31 Reset ........................................................................ 181 Restoring from exception/interrupt .............................. 44 Restoring from fatal exception routine ......................... 44 RXD ............................................................................ 34 [J] Judgment of on-page/off-page .................................... 94 [L] LLCAS ......................................................................... 32 LLMWR........................................................................ 30 Lockup time .............................................................. 170 LUCAS......................................................................... 32 LUMWR ...................................................................... 30 [M] Maskable interrupt ...................................................... 40 MRD............................................................................. 30 [N] NMI ............................................................................. 32 Non-maskable interrupt ...................................... 39, 181 [S] SCLK ........................................................................... 34 Selecting input clock ................................................. 170 Serial control signal .................................................... 33 Setting and operating status of HALT mode.............. 174 Setting and operating status of STOP mode ............. 176 SI ................................................................................. 34 [O] OE................................................................................ 32 190 APPENDIX B GENERAL INDEX Single transfer mode .................................................110 SO ................................................................................34 SRAM (ROM) cycle .....................................................53 Standby mode ...........................................................173 STOP mode................................................................176 System control signal ...................................................31 [X] X1, X2 ..........................................................................31 [T] TC ................................................................................33 TCLR ...........................................................................33 Temporary stop by HLDRQ signal or refresh .............122 TI .................................................................................33 Timer 1 ......................................................................149 Timer 4 .......................................................................151 Timer control register 1 ..............................................156 Timer control register 4 ..............................................157 Timer output control register ......................................158 Timer overflow status register ...................................159 Timer unit mode register ............................................154 Timer/counter control register.....................................154 TMC1..........................................................................156 TMC4..........................................................................157 TO10.............................................................................33 TO11.............................................................................33 TOC1 ..........................................................................158 TOVS .........................................................................159 Transfer mode ...........................................................110 TRCDATA0 through TRCDATA3..................................34 TUM1 .........................................................................154 TXD .............................................................................33 [U] UART..........................................................................125 ULCAS..........................................................................32 ULMWR ........................................................................30 UUCAS .........................................................................33 UUMWR .......................................................................31 [V] VDD................................................................................28 VDD_PLL .......................................................................28 [W] Wait control by READY pin...........................................92 Wait control register .....................................................87 WE................................................................................33 191 [MEMO] 192 Facsimile Message From: Name Company Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation. Please complete this form whenever you'd like to report errors or suggest improvements to us. Tel. FAX Address Thank you for your kind support. North America Hong Kong, Philippines, Oceania NEC Electronics Inc. NEC Electronics Hong Kong Ltd. Corporate Communications Dept. Fax: +852-2886-9022/9044 Fax: 1-800-729-9288 1-408-588-6130 Korea Europe NEC Electronics Hong Kong Ltd. NEC Electronics (Europe) GmbH Seoul Branch Technical Documentation Dept. Fax: 02-528-4411 Fax: +49-211-6503-274 South America NEC do Brasil S.A. Fax: +55-11-6465-6829 Taiwan NEC Electronics Taiwan Ltd. Fax: 02-2719-5951 Asian Nations except Philippines NEC Electronics Singapore Pte. Ltd. Fax: +65-250-3583 Japan NEC Semiconductor Technical Hotline Fax: 044-548-7900 I would like to report the following error/make the following suggestion: Document title: Document number: Page number: If possible, please fax the referenced page or drawing. Document Rating Clarity Technical Accuracy Organization CS 98.8 Excellent Good Acceptable Poor |
Price & Availability of UPD705101GM-100-8ED
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |